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The overall architecture of FPGA chips is shown below, generally divided by clock domains, based on different processes, device speeds, and corresponding clocks:
The detailed internal architecture of FPGA is further divided into the following six major modules:
1. Programmable Input Output Block (IOB)
To facilitate management and adapt to various electrical standards, the IOB of FPGA is divided into several groups (Banks), with each Bank’s interface standard determined by its interface voltage VCCO. A Bank can only have one VCCO, but different Banks can have different VCCOs. Only ports with the same electrical standards and physical characteristics can be connected together, and the same VCCO voltage is a basic condition for the interface standard.
2. Configurable Logic Block (CLB)
The basic programmable logic unit of FPGA is the CLB, which consists of lookup tables, data selectors, carry chains, and registers. The lookup tables and multiplexers complete combinational logic functions, while registers (configurable as flip-flops or latches) complete sequential logic functions. In Xilinx FPGA devices, a CLB is composed of multiple (generally 4 or 2) identical slices and additional logic.
Slices are further divided into SLICEL (Logic) and SLICEM (Memory). Both SLICEL and SLICEM each contain 4 six-input lookup tables (LUT6), 3 data selectors (Mux), 1 carry chain (Carry Chain), and 8 flip-flops (Flip-Flop):
Lookup Table: A six-input lookup table is similar to a ROM with a capacity of 64 bits (26 = 64) (a precious SRAM resource in terms of technology). The 6 indicates the address input width of 6 bits, and the stored content corresponds to the logical operation result of the input, which is loaded during FPGA configuration.
For lookup tables: Currently, mainstream FPGAs use LUT (Look Up Table) structures based on SRAM technology.LUT is essentially a RAM. When users describe a logic circuit using schematics or HDL languages, the FPGA development software automatically calculates all possible results of the logic circuit, lists them in the form of a truth table, and writes the truth table (i.e., the logical outputs corresponding to the inputs) into the RAM in advance. Thus, every time an input signal is processed for logical operations, it is equivalent to inputting an address to look up the table, finding the content corresponding to the address, and then outputting it.Currently, FPGAs mostly use 4-input LUTs, so each LUT can be seen as a RAM with 4 address lines.
Data Selector: Data selectors are generally fixed after FPGA configuration. Carry Chain: A carry chain facilitates the implementation of adders and speeds up complex addition operations. Registers: Can be configured in various working modes, such as FF or Latch, synchronous reset or asynchronous reset, high or low effective reset, etc. The structure of SLICEM is similar to that of SLICEL, with the main difference being that a new unit replaces the lookup table in the SLICE. This new unit can be configured as LUT, RAM, ROM, or shift registers (SRL16 or SRL32), thereby achieving the logical functions of LUT, as well as serving as storage units (multiple units combined can provide greater capacity) and shift registers (providing delay functions, etc.).
In SLICEM, the input addresses and write addresses for LUT are both 8 bits, with the top two bits possibly used to connect 4 LUTs in parallel as a larger RAM or ROM, while LUTs in both SLICEL and SLICEM can be set as 5-bit or 6-bit lookup tables.
3. Block RAM (BRAM)
Block RAM can be configured as ROM, RAM, and FIFO and other commonly used storage modules. It differs from Distributed RAM (which is primarily composed of LUT and does not occupy BRAM resources). Distributed RAM can also be configured as ROM, RAM, and FIFO, but its performance is inferior to that of BRAM, as BRAM is dedicated memory. Generally, distributed RAM is only used when BRAM resources are insufficient. On the other hand, BRAM consists of a fixed number of blocks of a certain size, using BRAM resources does not occupy additional logic resources, and it is fast. However, the consumed BRAM resources must be integer multiples of its block size; even if you only store 1 bit, it will occupy one BRAM.
The Logic Cell Array (LCA) used in FPGA includes configurable logic modules CLB (Configurable Logic Block), input-output modules IOB (Input Output Block), and internal interconnects (Interconnect). The first two have been introduced, and now we will introduce the third:
4. Interconnect Resources
Wiring resources connect all units inside the FPGA, and the length and technology of the wires determine the driving capability and transmission speed of the signals on the wires. The FPGA chip has rich wiring resources, which are divided into 4 different categories based on technology, length, width, and distribution: the first category is global wiring resources, used for global clock and reset/reset wiring inside the chip; the second category is long line resources, used to complete high-speed signals between chip Banks and the second global clock signal wiring; the third category is short line resources, used to complete logical interconnections and wiring between basic logic units; the fourth category is distributed wiring resources, used for dedicated clock, reset, and other control signal lines.
5. Embedded Functional Units
The embedded functional modules mainly refer to DLL (Delay Locked Loop), PLL (Phase Locked Loop), DSP (Digital System Processing), DCM (Digital Clock Manager) (providing digital clock management and phase-locked loops), and CPU (Central Processing Unit), etc. soft processing cores (such as the soft core of MicroBlaze). The increasingly rich embedded functional units have made single-chip FPGA a system-level design tool, enabling it to possess the capability of hardware-software co-design, gradually transitioning to SoC platforms.
Regarding DCM: DCM is an important device for processing clocks inside FPGA, and its main functions are three: eliminating clock skew, frequency synthesis, and phase adjustment.
The core device of DCM is the digital phase-locked loop (DLL, Delay Locked Loop). It consists of a series of fixed-delay delay lines, each with a delay of 30 picoseconds, meaning that the precision of frequency multiplication, division, and phase adjustment performed by DCM is 30 picoseconds.
For clocks, it is best not to connect two clocks through an AND gate or OR gate (logical operation), as this may produce glitches that affect system stability. If you need to operate on the clock, such as switching clocks, please use the dedicated device “BUFGMUX” inside the FPGA.
6. Embedded Dedicated Hard Cores
Embedded dedicated hard cores refer to hard cores (such as the ARM Cortex-A9 hard core) with strong processing capabilities, which are equivalent to ASIC circuits. To improve FPGA performance, chip manufacturers integrate some dedicated hard cores inside the chip. For example, to enhance the speed of multiplication in FPGA, mainstream FPGAs integrate dedicated multipliers, and to adapt to communication buses and interface standards, many high-end FPGAs integrate serial/parallel transceivers (Serdes), achieving transceiving speeds of several tens of Gbps (such as FMC).
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