The content of interrupt priorities includes general urgent interrupts and particularly urgent interrupts, which depend on the specific system design. This involves the concepts of interrupt priority and interrupt nesting. Today, we will briefly introduce the relevant registers without providing example code.
The background of interrupts can be more complex in real life. For example, while I am watching TV, I receive a phone call, and I need to enter the “interrupt” routine for answering the call. At the same time, I hear the sound of boiling water, which also triggers an “interrupt.” I must put down the phone to turn off the gas before returning to the call, and only after finishing the call can I resume watching TV. This creates a priority issue.
In another scenario, while watching TV, I hear the sound of boiling water, which triggers the “interrupt” to turn off the gas. While turning off the gas, the phone rings. In this case, our approach is to first turn off the gas, then answer the phone, and finally return to watching TV.
From these two processes, we can conclude that when the most urgent matter occurs, regardless of which “routine” we are in, we must first address the most urgent issue. After handling it, we can then resolve other matters.
In our microcontroller programs, there are sometimes general urgent interrupts and particularly urgent interrupts, depending on the specific system design. This involves the concepts of interrupt priority and interrupt nesting. Today, we will briefly introduce the relevant registers without providing example code.
There are two types of interrupt priorities: preemptive priority and inherent priority. First, let’s introduce preemptive priority. See Table 1 and Table 2.
Table 1:IP – Interrupt Priority Register Bit Allocation (Address 0xB8, bit-addressable)
Table 2:IP – Interrupt Priority Register Bit Description
Each bit of the IP register represents the preemptive priority of the corresponding interrupt. The reset value of each bit is 0. When we set a certain bit to 1, its priority becomes higher than that of other bits.
For example, after we set the PT0 bit to 1, when the microcontroller is executing in the main loop or any other interrupt routine, if Timer T0 generates an interrupt, due to its higher priority, the program will immediately jump to the T0 interrupt routine.
Conversely, when the microcontroller is executing the T0 interrupt routine, if another interrupt occurs, it will continue executing the T0 interrupt routine until it is completed before handling other interrupts.
When executing a low-priority interrupt, if a high-priority interrupt occurs, the system will immediately enter the high-priority interrupt routine. After handling the high-priority interrupt, it will return to handle the low-priority interrupt. This process is called interrupt nesting, also known as preemption.
Thus, the concept of preemptive priority is that a higher-priority interrupt can interrupt the execution of a lower-priority interrupt, forming a nested structure. Conversely, a lower-priority interrupt cannot interrupt a higher-priority interrupt.
Table 3:Interrupt Query Sequence
Since there is preemptive priority, there is naturally also non-preemptive priority, also known as inherent priority. The last column in Table 3 shows the inherent priority. Note that in the numbering of interrupt priorities, generally, the smaller the number, the higher the priority.
From Table 3, we can see that there are a total of 6 levels of priority from 1 to 6. The difference between this priority and preemptive priority is that it does not have the characteristic of preemption. This means that even if a high-priority interrupt occurs during the execution of a low-priority interrupt, the high-priority interrupt can only be responded to after the low-priority interrupt has finished executing. Since it cannot preempt, what is the use of this priority?
The answer is arbitration when multiple interrupts exist simultaneously. For example, if multiple interrupts occur at the same time, the probability of this happening is low in practice. However, another common situation is that for some reason, we temporarily disable all interrupts (EA=0), and after executing a segment of code, we re-enable all interrupts (EA=1). During this time, it is very likely that multiple interrupts have occurred, but since all interrupts are disabled, they do not get responded to. When all interrupts are re-enabled, they will all request a response simultaneously. Clearly, there must be a sequence in which they are handled, which is the role of non-preemptive priority. As shown in Table 3, the highest priority interrupt responds first, and then they are queued in order of their numbers for response.
The collaboration of preemptive and non-preemptive priorities allows the microcontroller interrupt system to operate in an orderly manner, ensuring that urgent tasks are prioritized when necessary without endless nesting. In the subsequent learning process, the interrupt system will be ever-present, and as you delve deeper into the subject, your understanding will also deepen.
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