This article mainly introduces the speed grade parameter when selecting an FPGA.

• The speed grade of the chip is determined by the internal gate delay and line delay of the chip, which depend on the length L and capacitance C of the transistors; the differences in these two values ultimately depend on the chip manufacturing process.

• There is a stage in the chip production process called speed binning. It filters and classifies the produced chips according to certain methods and standards, thereby dividing them into different speed grades.

• The calibration of the speed grade depends not only on the quality of the chip itself but also on the market positioning of the chip; the probability of rework and cost are also factors.

• The chip’s grade can be adjusted and improved after testing; this technology is widely used in the production of memory chips.

• The chip production process is full of various uncertainties; the production process can be controlled, but control cannot be precise to a molecule or an atom, and product quality can only be a statistical target. There will be variations among chips on the same wafer, and even different parts of the same chip will have variations. The speed grade is a statistical figure that reflects certain common characteristics of a batch of chips and does not represent the quality of individual chips. Moreover, since some chips are tested on a sample basis, it cannot be ruled out that individual chips may perform below the calibrated speed grade. However, FPGA testing is extremely strict, and it is very likely that the chips we receive have all undergone detailed testing. This is also the reason why FPGA chips are priced higher than ordinary chips.

• Most chips of the same grade should perform better than the speed grade division standards. This is also why in FPGA design, a few designs that violate timing analysis can still run normally when downloaded to the chip (the model parameters used in timing analysis are statistical parameters of the chip, which are the most conservative and safest). However, since there are still performance differences among chips of the same grade, FPGA designs that violate timing but pass a single test cannot ensure that there will be no issues in mass production on individual chips (if issues arise, rework or on-site investigation is required, which significantly increases costs). Therefore, timing must be closed to ensure mass production; this is the engineering standard that guarantees product quality.

• The real world is analog, not digital. When examining real-world problems, digital engineers and software engineers should abandon the notion of “one is one, zero is zero” and view this continuously changing real world with a continuous perspective.

• The uncertainties in the chip production process lead to performance differences among chips, which affect the price of the chips; the trade-off between price and performance also influences FPGA design engineers’ decisions regarding device selection and design methods; the cost-effectiveness of the produced products determines their sales, and product sales determine the chip procurement volume, which in turn affects the chip procurement price…

• Due to transmission line effects, high-speed devices are more prone to signal reflections, requiring more effort to maintain signal integrity in design.

• High-speed devices are generally used less frequently, and their prices often increase exponentially; moreover, the supply channels for high-speed devices are usually limited, and the ordering cycle for these devices is generally longer, which extends the product development cycle and reduces the product’s market entry rate.

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