The evolution of embedded system design methods is mainly driven by application demands and IT technology advancements. With continuous innovation and development in microelectronics technology, the integration and process levels of large-scale integrated circuits have been continuously improved. The combination of silicon materials and human intelligence has produced a large number of low-cost, high-reliability, and high-precision microelectronic structure modules, promoting the development of a brand new technology field and industry.
The devices developed on this basis can change and implement hardware functions through software, thanks to the programmable ideas and microprocessor technology. The extensive application of microprocessors and various programmable large-scale integrated circuits and semi-custom devices has created a brand new application world that widely influences and gradually changes human production, life, and learning activities.
The significant improvement in computer hardware platform performance has made many complex algorithms and user-friendly interfaces possible, greatly enhancing work efficiency and providing a physical basis for the assisted design of complex embedded systems.
The development of high-performance EDA integrated development tools (platforms) has made great strides, and their level of automation and intelligence continues to improve, providing an integrated development environment that is easy to learn and convenient to use for complex embedded system design, covering various purposes and different levels of editing, layout, wiring, compilation, integration, simulation, testing, verification, and device programming.
The development of Hardware Description Language (HDL) has provided a working medium for establishing various hardware models in complex electronic system design. Its strong description and abstraction capabilities have brought significant changes to hardware circuits, especially in the design of semi-custom large-scale integrated circuits. Currently, commonly used HDLs include VHDL, which has become the IEEE STD1076 standard, Verilog HDL, which is IEEE STD 1364 standard, and AHDL, which is the corporate standard of Altera.
Due to the development and standardization of HDL, a number of companies specializing in the functional design of various integrated circuit functional modules using HDL have emerged worldwide. Their task is to describe the functions and structures of integrated circuits using HDL according to common or specific functions, and to form different levels of IP core modules through verification at different levels for chip designers to assemble or integrate.
IP (Intellectual Property) core modules are pre-designed, even verified integrated circuits, devices, or components with specific functions. They come in several different forms. IP core modules have three levels of design: behavior (behavior), structure (structure), and physical (physical), corresponding to the soft IP core that mainly describes functional behavior, the firm IP core that completes structural description, and the hard IP core that is based on physical description and verified by technology. This is equivalent to the design technology of integrated circuits (devices or components) in their raw, semi-finished, and finished states.
Soft IP cores are generally submitted to users in some HDL text, optimized for behavioral design and functional verification, but contain no specific physical information. Therefore, users can synthesize the correct gate-level netlist and carry out subsequent structural design, offering maximum flexibility. They can easily integrate with other external logic circuits using EDA synthesis tools, designing devices with different performances according to various semiconductor processes. Commercializable soft IP cores typically have a total gate count exceeding 5000 gates. However, if subsequent designs are poorly executed, it may lead to total failure. Soft IP cores are also referred to as virtual devices.
Hard IP cores are based on the physical design of a certain semiconductor process, with fixed topology layout and specific processes, and have been verified by technology, ensuring performance. The form provided to users is the circuit physical structure mask layout and a complete set of process documents, which can be used immediately.
The design depth of firm IP cores lies between soft IP cores and hard IP cores. In addition to completing all designs of hard IP cores, it also completes design steps such as gate-level synthesis and timing simulation, generally submitted to users in the form of gate-level netlists.
Manufacturers such as TI, Philips, and Atmel have developed unique microcontrollers compatible with Intel’s MCS51 by using Intel’s authorized MCS51 IP core modules combined with their own strengths.
Commonly used IP core modules include various CPUs (32/64-bit CISC/RISC structure CPUs or 8/16-bit microcontrollers, such as 8051), 32/64-bit DSPs (such as 320C30), DRAM, SRAM, EEPROM, Flash memory, A/D, D/A, MPEG/JPEG, USB, PCI, standard interfaces, network units, compilers, encoders/decoders, and analog device modules. A rich library of IP core modules provides a basic guarantee for the rapid design of dedicated integrated circuits and single-chip systems, as well as for quickly capturing the market.
Advances in software technology, especially the introduction of Embedded Operating Systems (EOS), have provided underlying support and a high-efficiency development platform for developing complex embedded system application software. EOS is a powerful, widely applicable real-time multitasking system software. It generally has various system resource management functions typical of operating systems, and users can manage resources through application program interface (API) function calls. User programs can be developed and run on the basis of EOS. Compared to the OS in general systems, it is characterized by a compact and efficient system kernel, low overhead, strong real-time capabilities, and high reliability. A complete EOS also provides drivers for various devices. To adapt to network applications and Internet applications, it can also provide TCP/IP protocol support. Currently popular EOS include 3Com’s Palm OS, Microsoft’s Windows CE and Windows NT Embedded 4.0, Tokyo University’s Tron, various open-source embedded Linux distributions, as well as domestic successful developments such as Hopen OS from Kaisi Group and HBOS from Zhejiang University.
In the past, software design programmers generally kept their distance from hardware circuit design, considering hardware design and software design as completely different technologies.
With the development of electronic information technology, designers with an electronics engineering background have gradually ventured into software programming. The main form is learning relevant assembly language programming through the application of microcontrollers (commonly referred to as single-chip computers in China). When designing large-scale distributed control systems, the commonly used PC is inevitably employed as the upper machine, leading to further learning of high-level language programming such as Quick BASIC, C, C++, VC, and VB to create system programs and design system interfaces, forming a centralized distributed control system through multi-machine communication with the front-end controlled by microcontrollers.
Designers with a background in software programming are rarely interested in learning circuit design applications. However, with the rapid development of computer technology, especially the invention of Hardware Description Language (HDL), the methods of system hardware design have changed. The hardware composition and behavior of digital systems can now be fully described and simulated using HDL. In this case, designing hardware circuits is no longer the exclusive domain of hardware design engineers; designers skilled in software programming can use HDL tools to describe the behavior, functions, structures, data flows, signal connections, and timing relationships of hardware circuits, designing hardware systems that meet various requirements.
EDA tools allow for two types of design input tools, catering to the needs of hardware circuit designers and software programmers from different backgrounds. Designers with a hardware background can use the schematic input method they are accustomed to, while those with a software background can use the hardware description language input method. Since HDL descriptions are used for input, they are closer to system behavior descriptions, easier for synthesis, timing analysis, and modification, and can establish design files independent of the process. Therefore, once software programmers master HDL and some necessary hardware knowledge, they can often design better hardware circuits and systems than engineers accustomed to traditional design. Thus, engineers used to traditional design should learn to describe and program using HDL.
There are three different levels of embedded system design:
Level 1: Design Method Primarily Using PCB CAD Software and ICE
This is the method that has been used by embedded system designers in China for single-chip applications from the past to the present, with steps that follow abstraction before specificity.
Abstract design mainly involves refining the functional requirements of the embedded application system, dividing it into several functional modules, drawing the system functional block diagram, and then allocating the implementation of hardware and software functions for each functional module.
Specific design includes hardware design and software design. Hardware design mainly involves selecting and combining the components needed for each functional module according to performance parameter requirements, with the basic principle being to choose the most cost-effective general-purpose components available on the market. If necessary, each uncertain part must undergo testing, functional verification, and performance testing, finding relatively optimized solutions from module to system, and drawing the circuit schematic. A key step in hardware design is using PCB computer-aided design (CAD) software to layout and route the components of the system, followed by PCB processing, assembly, and hardware debugging.
The most labor-intensive part is software design. Software design runs throughout the entire system design process, mainly involving task analysis, resource allocation, module division, flow design and refinement, coding, and debugging. The workload of software design mainly focuses on program debugging, so debugging tools are crucial. The most commonly used and effective tool is the in-circuit emulator (ICE).
Level 2: Design Method Based on EDA Tool Software and EOS Development Platform
With the development of microelectronics process technology, various general-purpose programmable semi-custom logic devices have emerged. During hardware design, designers can utilize these semi-custom devices to gradually convert several standard logic devices that previously needed to be interconnected through PCB wiring into application-specific integrated circuits (ASICs), thus transforming the complexity of PCB layout and wiring into the complexity of configurations within semi-custom devices.
However, designing semi-custom devices does not require designers to have knowledge and experience in semiconductor processes and integrated circuit layout and wiring. As the scale of semi-custom devices increases and the number of devices that can be integrated grows, the costs of wiring, assembly, and debugging on PCBs decrease significantly, greatly reducing PCB area and the number of connectors, lowering overall system costs, increasing flexibility for programmable applications, and most importantly, reducing system power consumption and improving system operational speed, significantly enhancing system reliability and safety.
Thus, hardware designers are gradually shifting from the selection and use of standard general-purpose integrated circuit devices to designing and producing some specific integrated circuit devices, with support from various EDA tool software.
Semi-custom logic devices have undergone a development process from programmable logic arrays (PLA), programmable array logic (PAL), generic array logic (GAL), complex programmable logic devices (CPLD), to field-programmable gate arrays (FPGA). The trend is for integration levels and speeds to continually improve, functionalities to enhance, structures to become more rational, and usage to become more flexible and convenient.
Designers can use various EDA tools and standard CPLD and FPGA devices to design and produce user-specific large-scale integrated circuits. They can then layout and route the integrated circuits designed using semi-custom devices, programmable peripheral devices, and selected ASICs with embedded microprocessors or microcontrollers on PCBs using a bottom-up design methodology.
Level 3: Design Method Based on IP Core Libraries, Using Hardware-Software Co-Design Techniques
Since the 1990s, there has been a continuous shift from “integrated circuit” level design to “integrated system” level design. We have now entered the stage of single-chip system (SoC) design, which has begun to enter practical application. This design method does not simply integrate all the integrated circuits needed for the system onto one chip; if this were the case, achieving the high density, high speed, high performance, small size, low voltage, and low power consumption required for single-chip systems would be impossible, especially the low power consumption requirement.
Single-chip system design must start from the overall system performance requirements, tightly integrating the designs of microprocessors, model algorithms, chip structures, and peripheral device circuits down to the device level, and completing the entire system’s functionality on a single chip through a new concept of co-design between system software and hardware. Sometimes, the system may also be implemented across several chips, as not all systems can be realized on a single chip, and some may not be commercially viable due to high process costs. Currently, practical single-chip systems are still relatively simple, such as smart IC cards. However, several well-known semiconductor manufacturers are intensively researching and developing complex single-chip systems like single-chip PCs.
If single-chip system design starts from scratch, it is neither realistic nor necessary. This is because immature designs that have not been time-tested cannot guarantee system performance and quality, and lengthy design cycles may lead to the loss of commercial value.
To accelerate the single-chip system design cycle and improve system reliability, one of the most effective approaches is to use mature, optimized IP core modules for design integration and secondary development through licensing, utilizing Glue Logic Technology (GLT) to embed these IP core modules into SoCs. IP core modules serve as the foundation for single-chip system design. The decision on which level of IP core module to purchase should be weighed against existing foundations, time, funding, and other conditions.
Purchasing hard IP core modules carries the least risk but incurs the highest costs. However, overall, purchasing IP core modules can not only reduce development risks but also save development costs, as the cost of purchasing IP core modules is generally lower than the costs of designing and verifying them independently. Of course, not all required IP core modules are available in the market. To monopolize the market, some companies develop key IP core modules that they are unwilling to authorize for transfer at least temporarily. In such cases, it becomes necessary to organize internal resources for development.
These three levels each have their own application scopes. From an application development perspective, for a considerable period, the first two methods will be adopted. The third level design method can only be used by general application personnel for simple single-chip systems. Complex single-chip systems can only be designed and implemented by certain large semiconductor manufacturers, and the single-chip systems realized using this method are only worthwhile to develop for widely used, scalable application systems. Some application systems may not be suitable for single-chip realization due to technical or commercial value issues. Once these products are launched as commercial single-chip systems, application personnel only need to know how to select them.
Thus, the three design methods will coexist and will not simply replace each other. Junior application designers will primarily use the first method; experienced designers will mainly use the second method; and highly specialized designers will apply the third method for simple single-chip system design and applications. However, all designers can utilize specialized single-chip systems designed by major semiconductor manufacturers using the third method.
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