If you are a heavy command line user, learning Makefile can greatly improve your development efficiency. Below is a brief introduction to the knowledge and usage of Makefile.
Makefile is a file that contains a set of instructions for compiling and building software projects.
A Makefile typically contains a set of rules and dependencies that specify how to compile source code into executable files or libraries.
When the make command is executed, the make tool parses the Makefile and performs the necessary operations based on the defined rules and dependencies to generate the final target files.
Makefile is a commonly used build tool, especially prevalent in Unix and Linux systems.
A Makefile consists of a series of rules. The format of each rule is as follows.
Rule Syntax
target ... : prerequisites ...
command
...
The part before the colon on the first line is called the “target”; the part after the colon is called the “prerequisites”;
The second line must start with a tab character, followed by the “commands”.
The “target” is mandatory and cannot be omitted; both “prerequisites” and “commands” are optional, but at least one of the two must exist.
Each rule clearly states two things: what the prerequisites for building the target are, and how to build it.
Now let’s explain in detail the three components of each rule.
Example File
.PHONY: test # .PHONY is a phony target, meaning that the make test command will be executed regardless of whether the test file or directory exists.
txt = Hello World # Makefile allows using equals sign to define variables.
all: clear test php # When executing make without other commands, the first one is executed by default.
python:
-python vv # Adding - in front of the command means to continue executing the following commands even if an error occurs.
php -v # The hash symbol (#) in Makefile indicates a comment.
php:
@php -v # Normally, make prints each command before execution, which is called echoing. Adding @ before the command can turn off echoing.
clear:
clear
test:
@echo $(txt) # Using variables
@echo =============
This is a relatively concise article, hoping to give you a basic understanding of Makefile.
Makefile Tutorial: https://seisman.github.io/how-to-write-makefile/index.html