RISC-V International is a non-profit organization responsible for maintaining and developing the RISC-V open instruction set architecture (ISA) and promoting the construction of its global ecosystem.
1. Historical Origins
(1) 2010
Fifteen years ago, a bold idea was born in a university laboratory: What changes would occur if chip design could become more open, allowing more people to participate and innovate? What if a modern, open standard instruction set architecture (ISA) could empower global engineers and innovators, freeing them from proprietary licensing constraints? This idea gave birth to RISC-V.
At the University of California, Berkeley’s Parallel Computing Laboratory (Par Lab), anticipating demand, Professor Krste Asanović and graduate students Andrew Waterman and Yunsup Lee (who later co-founded SiFive) decided to create a simple, flexible, and most importantly, “open” instruction set architecture, with the support of David Patterson, known as the “father of RISC”.
(2) 2011
On May 13, the “The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA” was released (Technical Report No. UCB/EECS-2011-62). This document defined the basic user-level instruction set RISC-V’s 32-bit base integer instruction set (RV32I), which includes 47 instructions, adopts a modular design concept, and supports subsequent extensions (such as multiplication and division “M”, atomic operations “A”, etc.). It was designed as an open instruction set for research and educational purposes, using the BSD open-source license, allowing free use and modification.
(3) 2014
The Berkeley team officially launched the fifth-generation RISC-V architecture (“V” represents the Roman numeral 5) and released the complete user-level ISA specification.
Its distinction lies in the fact that RISC-V can be designed from scratch, avoiding the historical baggage and proprietary complexities of traditional architectures. This historically significant revolutionary new ISA can scale from low-power embedded devices to high-performance data center workloads.
(4) 2015—2021
In 2015, the Berkeley team, in collaboration with the industry, established the RISC-V Foundation (a non-profit organization) headquartered in Delaware, USA; RISC-V began to enter the embedded market, with SiFive’s success proving its commercial viability; Yunsup Lee, Krste Asanović, and Andrew Waterman co-founded SiFive, aiming to provide processor IP and customized chip solutions based on RISC-V.
In 2016, SiFive released the first commercial RISC-V chip, the “Freedom” series, including the FE310 (embedded microcontroller).
In 2017, the RISC-V specifications were further standardized, and an updated version of “The RISC-V Instruction Set Manual” was released.
In 2018, SiFive launched more powerful RISC-V cores (such as U54 and U74), supporting Linux operation.
In 2020, due to geopolitical risks (U.S. technology export controls), the organization moved from Delaware to Switzerland and was renamed RISC-V International to ensure a neutral and independent global open standard.
In 2021, the RISC-V extensions (such as vector extension RVV1.0) were officially frozen and became part of the standard; RISC-V was adopted by major companies such as NVIDIA and Western Digital, significantly expanding the ecosystem.
2. Core Mission and Goals of RISC-V International
Open Standard: RISC-V ISA is royalty-free, allowing anyone to freely use, modify, and implement it.
The RISC-V ISA architecture is an open international standard that specifies the interface between computer software and hardware. It serves as a shared language, setting parameters for communication and interoperability. The open standard provides a means for industry participants to collaborate and develop technical solutions, helping to accelerate innovation and limit the abuse of intellectual property (IP).
Ecological Development: Supporting the comprehensive development of hardware, software, toolchains, and applications.
Global Collaboration: Bringing together enterprises, academic institutions, and developers to jointly promote the evolution of RISC-V.
3. RISC-V in the ISA Landscape
Currently, two leading semiconductor instruction set architectures (ISAs) dominate most of the market: x86 (from the U.S. Intel/AMD) and ARM (from the U.K. Arm Holdings, which is controlled by Japan’s SoftBank Group).
ISAs mainly fall into two categories: Complex Instruction Set Computer (CISC) and Reduced Instruction Set Computer (RISC), which differ in organization and operational efficiency; x86 is based on CISC principles, while ARM is based on RISC. Most laptops and desktop computers use the x86 ISA, while ARM holds nearly the entire market share in the mobile sector. The ARM and Intel/AMD ISAs are proprietary standards, meaning other companies and designers can license ARM IP or purchase and use processors based on Intel/AMD IP.
In contrast, the latest entrant in the field is RISC-V, an open standard ISA based on RISC principles, allowing chip design teams to access and implement it freely across various use cases without licensing restrictions. In other words, RISC-V allows for easy customization through royalty-free licensing and imposes no licensing restrictions on modifications.
4. Key Advantages of RISC-V
(1) Flexibility and Accessibility
The flexibility and accessibility of RISC-V make it an extremely attractive and rapidly growing ISA. Early use cases were primarily focused on the embedded systems market, with potential applications in high-performance computing (HPC), artificial intelligence (AI), consumer electronics, and wearable devices. Currently, the number of RISC-V-based chips has exceeded 2 billion, and it is expected to grow to 20 billion by 2031. The number of members in RISC-V International has increased from 236 in 2019 to over 4,600 by 2025, as the organization is committed to leveraging this support.
At the end of 2019, geopolitical risks (U.S. technology export controls) prompted the RISC-V International organization to relocate its management from Delaware to Switzerland, with the rationale being to enable universities, governments, and enterprises outside the U.S. to access and develop its technology, ensuring technological neutrality. Since then, this non-profit organization has been building collaborative tools and opportunities within the ecosystem and has established 68 new specifications and over 80 working groups.
(2) Low-Cost, High-Control Platform
Many companies currently purchasing x86 or ARM ISA licenses are participating in the development of RISC-V to gain another semiconductor architecture option without paying high licensing fees. This allows engineers to implement their customizations on top of the ISA, thereby gaining better control over their technology and fully leveraging the software compatibility of the RISC-V ecosystem.
For example:
In 2022, Qualcomm announced a partnership with SiFive to develop RISC-V Snapdragon chips.
In 2023, Google Android officially supported RISC-V.
(3) Significant Advantages in AI
The ability of RISC-V to customize hardware for specific workloads (especially matrix and vector operations) is attracting many large enterprises.
Vector computing is becoming a foundational technology across various market sectors.
AI is a new field where almost all hardware designs require customization. RISC-V, as a system foundation, allows customers to focus on their areas of expertise and leverage proprietary extensions to gain advantages. RISC-V is being integrated into numerous areas of data centers and edge devices used for AI computing, creating significant opportunities for the RISC-V ecosystem.
(4) Secure IP Environment
RISC-V does not contain sensitive IP, and collaborative development does not require companies to disclose such IP.
The formulation of RISC-V standards does not require U.S. companies to share confidential information with other companies. Sensitive IP of companies is only used for their RISC-V implementations and is not shared through the RISC-V platform itself, and companies can license their RISC-V implementations. For example, startups like SiFive and Tenstorrent use the RISC-V ISA and then license their implementations as IP.
Additionally, some believe that open-source ISA designs are more secure than closed designs because they allow members of the technology community to collaboratively identify vulnerabilities.
5. Technical Committees of RISC-V International
The technical committees and working groups create and maintain hardware ISAs, testing and debugging frameworks, software specifications, and other technical aspects.
(1) Key Working Groups
Base ISA (Unprivileged/Privileged): Defines core instructions and privileged architectures (such as S/U/M modes).
Extension Working Groups: Such as vector extensions (RVV), scalar cryptography (Scalar Crypto), DSP/AI extensions.
Security Working Group: Develops Trusted Execution Environment (TEE) standards.
Operating Systems and Toolchains: Supports Linux, RTOS, LLVM/GCC, etc.
(2) Industry Distribution of RISC-V International Members
The focus on computing and cloud services (Computing & Cloud): accounts for 49.5%, dominating the market, indicating that RISC-V is being used in high-performance scenarios such as data centers and edge computing (e.g., Ventana’s server chips).
Academic and industrial collaboration: The proportion of research institutions (10.9%) and chip/IP companies (totaling 9%) highlights the “industry-academia-research” integration characteristic of RISC-V.
Toolchain Shortcomings: IP & Tooling only account for 4.4%, reflecting that the RISC-V ecosystem still needs to strengthen EDA tool and development environment support.
Vertical industries still need to expand: Key sectors such as automotive and aerospace have low representation (not listed separately), which may be a growth direction for RISC-V in the future.
6. Development of RISC-V in China
(1) Initial Stage
In 2011, the first version of the RISC-V manual was released, and Chinese universities (such as Tsinghua University and the Institute of Computing Technology, Chinese Academy of Sciences) began to explore its potential.
In 2018, the China RISC-V Industry Alliance (CRVA) was established, marking the formal involvement of the industry, aiming to build a complete open-source chip ecosystem by 2030. This stage was primarily focused on academic research, with a few companies (such as Alibaba’s T-Head) beginning to attempt to develop processors based on RISC-V. The technical applications were concentrated in low-power embedded fields, such as the Internet of Things (IoT).
(2) Acceleration Stage (2019 – 2021)
Recognizing the risks of dependence on x86 and ARM, RISC-V emerged as an alternative solution due to its open-source and royalty-free characteristics.
In 2019, the Institute of Computing Technology, Chinese Academy of Sciences, launched the “Xiangshan” project, aiming to develop high-performance RISC-V processors. In 2020, Alibaba’s T-Head open-sourced the Xuantie series processors (E902, E906, C906, C910), promoting ecosystem development.
In 2021, RISC-V International moved to Switzerland, with Chinese companies increasing their influence (12 out of 22 senior members are Chinese companies). Technically, the “Xiangshan” project released the first generation “Yanqi Lake” processor (Nanhu), with a frequency of 1.5GHz, approaching the performance of ARM Cortex-A72.
(3) Industrialization Stage
Commercial implementation and ecosystem improvement, with government and enterprise collaboration accelerating its industrialization.
In 2022, over 10 billion RISC-V chips were shipped globally, with more than half manufactured in China.
In 2023, Shandong University deployed a 48-node, 3072-core RISC-V cloud server cluster, becoming the first commercial RISC-V cloud instance.
In 2024, the second generation “Nanhu” processor of the “Xiangshan” project is expected to tape out, with a frequency increase to 2GHz, supporting vector extensions (RVV 1.0).
(4) Maturity and Competition Stage (2025 – Future)
The 14th Five-Year Plan clearly supports open-source architectures, with local governments providing talent and industrial park support.
By March 2025, China is promoting the transition of RISC-V from low-end to high-end applications, competing with ARM and x86.
In 2025, the third generation “Kunming Lake” processor of the “Xiangshan” project is planned to be released, with simulated test frequencies reaching 3GHz, approaching the performance of ARM Neoverse N2, targeting data centers and high-performance computing (HPC). The number of patents held by Chinese manufacturers in RISC-V has surged (reaching 1,061 in 2023, compared to only 10 in 2018), and the ecosystem, including chip design, EDA tools, and software development, has begun to take shape.
7. Domestic Applications of RISC-V
Currently, the domestic RISC-V ecosystem can be seen as a vibrant industry landscape with extensive participation from various manufacturers.
Large Enterprises: Alibaba’s T-Head launched the Xuantie C920 in 2023, claiming single-core performance comparable to ARM Cortex-A76. Huawei is also testing RISC-V architecture in some low-power scenarios.
Emerging Startups: Companies like Nuclei System and StarFive are focusing on RISC-V processor design, covering a range of applications from MCUs (microcontrollers) to server chips.
Traditional Chip Companies Transitioning: Companies like ZhiDong Microelectronics and GigaDevice are gradually integrating RISC-V into their product lines.
Conclusion
Currently, the domestic RISC-V camp can be seen as a reformer and challenger. China is also promoting the de-hegemony and decentralization of the global technology industry at the hardware level. The RISC-V architecture represents one of the future directions, driving the open computing revolution. All participants are builders of the new ecosystem and will be the owners in the future.
The above content is referenced from: https://riscv.org/
https://mp.weixin.qq.com/s/8g7yo3LUe1Qah51JG6JCvQ
https://mp.weixin.qq.com/s/bDvVqUwbF1xJz3wKPUjuKg
Written by | Zhang Ming
Typeset by | Kang Zexin
Reviewed by | Xu Dan, Chang Xiaoran
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