Introduction to NI MIMO Prototype Validation System Hardware

As the number of devices connected wirelessly continues to increase, there is an urgent need for wireless technologies that can meet higher data and capacity demands. The surge of Internet of Things (IoT) devices has placed a significant burden on existing wireless networks, and with the rise of video streaming and virtual reality technologies, the demand for data transmission rates exceeds what current rates can provide. Multi-Input Multi-Output (MIMO) technology is expected to address these issues by enabling a new generation of wireless technologies. By using multiple antennas, it is possible to transmit multiple data signals in the same time and frequency domain, greatly enhancing capacity, transmission rates, or stability simultaneously. As top researchers and wireless network companies urgently explore new communication technologies, MIMO is becoming a hot topic.

In particular, Multi-User MIMO (MU-MIMO) technology ensures a broad prospect for fifth-generation (5G) wireless networks. MU-MIMO allows base stations to utilize a large number of antennas, employing advanced signal processing techniques to simultaneously lock onto multiple users and reuse the same time and frequency space. MU-MIMO and Massive MIMO (a type of MU-MIMO) can increase wireless network capacity by more than ten times while providing greater reliability and network density.

While some of the basic principles of MU-MIMO and Massive MIMO are generally understood, researchers must establish real prototypes to innovate more rapidly. With the NI MIMO Prototype Validation System, researchers can prototype validate 5G MIMO systems and quickly obtain results.

The MIMO Prototype Validation System includes USRP RIO radios, FlexRIO FPGA co-processors, clock distribution modules, PCI Express routing hardware, and PXI Express chassis and controllers. This system can be configured in various sizes to meet customer needs. This article will detail various system components and configurations. For further information on application software, please refer to the MIMO Application Framework Technical White Paper.

USRP Software RadioUSRP RIO Software Radio (SDR) accelerates baseband processing tasks through an integrated 2×2 MIMO transceiver and high-performance Xilinx Kintex-7 FPGA, all housed in a half-width 1U rack-mountable chassis. Additionally, USRP RIO connects to the host controller via a PCI Express x4 cable linked to the system controller, transferring data to desktop or PXI Express host computers at speeds of up to 800 MB/s (or 200 MB/s to laptops via ExpressCard). Figure 1 shows a brief functional block diagram of the USRP RIO hardware.Figure 1. USRP RIO Hardware (a) and System Functional Block Diagram (b)

Wired PCI Express Switch BoxThe CPS-8910 wired PCI Express switch box (CPS) combines multiple USRP RIO PCI Express links into a single data stream, simplifying the system while effectively aggregating multiple channels. This switch box supports up to 8 independent downstream devices via a wired PCI Express x4 Gen 1 link. In MIMO configurations, these data streams are combined into a single PCI Express x8 Gen 2 link, achieving a total data transfer rate of up to 3.2 GB/s. In other configurations, a PCI Express x4 Gen 1 upstream link can be used. Additionally, the CPS-8910 provides point-to-point data streams between USRP devices. Both copper and fiber PCI Express cables are supported. Figure 2 shows a brief functional block diagram of the CPS-8910 hardware.Figure 2. Switch Box (a) and System Block Diagram (b)

PXI Express Chassis BackplaneThis system uses the PXIe-1085, an advanced 18-slot PXI chassis, with each slot equipped with PCI Express Gen 3 technology, suitable for high transfer rates and low-latency applications. This chassis provides 8 GB/s of bandwidth per slot and 24 GB/s of system bandwidth. Figure 3 shows the dual-switch backplane architecture.Figure 3. 18-Slot PXIe-1085 Chassis (a) and System Block Diagram (b)

High-Performance FPGA Co-ProcessorThe MIMO Prototype Validation System integrates a flexible high-performance FlexRIO FPGA processing module, programmable using the LabVIEW FPGA module of the PXI chassis. The PXIe-7976R FPGA module for FlexRIO can be used as a standalone device, providing a PCI Express x8 Gen 2 link connected to the PXI Express backplane for the large customizable Xilinx Kintex-7 410T.Figure 4. PXIe-7976R FlexRIO Module (a) and System Block Diagram (b)

Precise Clock GenerationThe PXIe-6674T synchronization module (Figure 5) features a high-accuracy onboard temperature-controlled quartz oscillator (OCXO), capable of generating a 10 MHz reference clock. This signal can establish a reference time base for each USRP RIO radio to ensure precise synchronization. The PXIe-6674T can also process and re-output the synchronization trigger signal from one of the USRP RIO SDRs.Figure 5. PXIe-6674T Timing and Synchronization Module

8-Channel Clock SynchronizationThe CDA-2990 8-channel clock distribution module can amplify and split the 10 MHz reference signal and second pulse signal in 8 ways through length-matched traces, providing frequency and time synchronization performance for up to 8 USRP devices. The CDA-2990 adds an internal timing and frequency reference via an integrated GPS disciplined oscillator (GPSDO). Figure 6 shows the system schematic of the CDA-2990 using GPSDO.Figure 6. CDA-2990 (a) and System Block Diagram (b)

The testbed formed by the combination of the above hardware components can expand the number of antennas from a few to 128 synchronized antennas. For simplicity, each example in this article uses a 128 antenna configuration.

Data ProcessingA high-channel-count MIMO system requires very stable data processing. Up to 128 channels of I and Q samples must be processed in real-time for transmission and reception. To handle such a large amount of data, the MIMO Prototype Validation System utilizes a high-throughput PCI Express bus. Data is transmitted from the USRP RIO SDR to a single PXI Express chassis via the PCI Express switch box. The chassis aggregates the data for centralized processing through the FPGA co-processor and the quad-core Intel i7 PXI controller. As shown in Figure 7, the PXIe-1085 chassis is the primary data aggregation node and real-time signal processing engine. Within slot 1 of the chassis, the PXIe-8135 RT controller serves as the central system controller. The PXIe-8135 RT is equipped with a 2.3 GHz quad-core Intel Core i7-3610QE processor (up to 3.3 GHz in single-core Turbo Boost mode). This chassis is additionally loaded with 8 PXIe-8384 (S1 to S8) remote control modules that connect the PCI Express switch box to the main system. Each switch box can thus aggregate 8 USRP RIO links. The link between the PXI chassis and the switch box uses PCI Express x8 Gen 2 technology, providing up to 3.2 GB/s performance between the main chassis and other switch boxes.

This system also features the PXIe-7976R FlexRIO FPGA co-processor module, which meets the real-time signal processing needs of the MIMO Prototype Validation System. Each PXIe-7976R uses a powerful Kintex-7 410T FPGA. Each FlexRIO module can receive or transmit data to each other through the backplane and can even connect to all USRP RIO SDRs; the latency of each FPGA co-processor is less than 5 microseconds, with a maximum transmission rate of 3.2 GB/s. The number of FlexRIO FPGA co-processors varies from 1 to 4, depending on the number of antennas used.Figure 7. Data Channel of the MIMO Prototype Validation System

Timing and SynchronizationCorrect timing and synchronization are critical for any MIMO system. The MIMO Prototype Validation System shares a 10 MHz reference clock and digital trigger, used to trigger the acquisition or generation functions of each radio to ensure system-level synchronization (Figure 8). The PXIe-6674T synchronization module in the chassis generates a highly stable and accurate 10 MHz reference clock (accuracy up to 80 ppb) via OCXO. This module also provides digital triggering for synchronization with devices attached to the host CDA-2990 clock distribution accessory. The host CDA-2990 is responsible for providing and caching the 10 MHz reference (MCLK) and trigger (MTrig) to the additional 8 CDA-2990 modules, which are then supplied to the USRP RIO SDR, ensuring that each antenna shares the 10 MHz reference clock and host trigger. Therefore, the aforementioned timing and synchronization architecture can very precisely control each radio/antenna element. This allows for phase coherent operation, maintaining stable phase shifts between channels. Software calibration techniques can be used to align channels properly.Figure 8. Clock Channel of the MIMO Prototype Validation System

The powerful testbed formed by the combination of data path hardware and timing modules can process large data flows in real-time and meet the synchronization needs of MIMO researchers. Additionally, this system itself is scalable. By slightly adjusting the hardware architecture, new antennas can be easily added.

User EquipmentIn MU-MIMO, multi-antenna base stations can communicate with several single-antenna instances of user equipment (UE). Each UE represents a mobile phone or other wireless device with wireless capabilities. Each UE can use a laptop GPSDO connected via a wired PCI Express to ExpressCard link. The GPSDO is crucial as it not only provides superior frequency accuracy but also offers synchronization and geolocation capabilities. A typical MU-MIMO testbed includes multiple independently operating USRP RIO SDRs as UEs. Since each USRP RIO SDR has 2 RF channels, each USRP combined with a laptop can represent 2 UEs.

The MIMO Prototype Validation System offers inherent flexibility and scalability to meet your needs. This system can handle 4-128 antennas (Figure 9).Figure 9. 128-Channel MU-MIMO Setup

As shown in Figure 10, the most common base station configurations include 16 antennas, 32 antennas, 64 antennas, and 128 antennas. If using the MIMO application framework, up to 12 UEs can be supported. However, the number of UEs cannot exceed the number of base station antennas minus one. The optimal performance is achieved when the ratio of base station antennas to UEs is 8:1.Figure 10. Common MU-MIMO Configurations

The actual configuration of MU-MIMO may vary depending on research requirements. For example, antennas provided by NI or custom-designed antennas can be used to interface with the radios. Larger MIMO systems that are fully assembled and rack-tested can also be purchased.

Although the MIMO Prototype Validation System can be completely designed from scratch using LabVIEW, this system is specifically designed to work with the MIMO Application Framework. The software architecture shown in Figure 11 provides an open, reconfigurable reference design that can be reconfigured based on research needs and can also serve as a foundation for new MIMO applications.Figure 11. Front Panel of the MIMO Application Framework

The MIMO Application Framework developed using the LabVIEW Communications System Design Suite supports immediately available MU-MIMO IPs, such as MMSE, MRC, and ZF beamforming. The MIMO Application Framework also provides wireless synchronization, channel reciprocity calibration, reconfigurable framework architecture, MIMO detection, precoding, and real-time communication capabilities. Please refer to the MIMO Application Framework White Paper for more information.

The MIMO Prototype Validation System is a flexible hardware testbed capable of providing 4 to 128 phase-coherent transceiver chains, supported by multiple powerful FPGAs for real-time processing. This system is an essential tool for prototyping and validating MIMO algorithms and technologies. The MIMO Application Framework significantly reduces the preparation work for prototyping MU-MIMO and massive MIMO systems. The core algorithms and IP of the MIMO Application Framework provide a well-validated and powerful structure for MU-MIMO systems, allowing users to avoid building the infrastructure from scratch. The MIMO Prototype Validation System, combined with the performance of the MIMO Application Framework, is an ideal platform for MIMO research, helping users innovate faster.