How STM32 Achieves Power Control

How STM32 Achieves Power Control Editor

The power control of STM32 is mainly achieved through the built-in Power Management Module (PWR), covering functions such as voltage regulation, power mode switching, and power monitoring. Below are its core mechanisms and implementation methods:

1. Power Architecture and Supply Areas

The power system of STM32 is divided into several supply areas, each with its own responsibilities:

Main Power (VDD) Operating voltage of 2.0-3.6V, supplying power to digital circuits, and stepping down to 1.8V through an internal voltage regulator for the core, memory, and peripherals (1.8V domain).

Analog Power (VDDA) Independently powers the ADC and reference voltage (VREF), reducing digital noise interference and improving conversion accuracy.

Backup Power (VBAT)

When VDD is powered off, the VBAT pin supplies power to the RTC, backup registers, and low-speed oscillator (LSE), ensuring that critical data is not lost. How STM32 Achieves Power Control

2. Voltage Regulator

The voltage regulator is the core of power control, supporting three operating modes:

Run Mode Full power output of 1.8V, all peripherals and core operate normally.

Stop Mode The regulator switches to low-power state, retaining the registers and SRAM data of the 1.8V domain, but turning off the clock to save power.

Standby Mode Completely shuts down the regulator, cutting power to the 1.8V domain, with only the backup domain and standby circuits maintaining power, resulting in the lowest power consumption.

3. Low Power Modes

STM32 provides three low power modes through the PWR module, arranged from high to low power consumption:

(1) Sleep Mode

Mechanism Only the CPU clock is turned off, while peripherals (such as USART, timers) continue to run.

Wake-up Method Any interrupt (WFI instruction) or event (WFE instruction) can wake it up, continuing execution from the paused state.

Application Scenario Short-term sleep with a need for quick response, such as intermittent data collection from sensors.

(2) Stop Mode

Mechanism All clocks (HSI/HSE/PLL) are turned off, retaining SRAM and register data, while the regulator can maintain a low-power state.

Wake-up Method Only supports external interrupts (such as EXTI) or RTC alarms for wake-up, requiring reconfiguration of the clock (e.g., calling <span>SystemInit()</span> to restore HSE).

Application Scenario Devices that need long-term sleep while retaining data, such as battery-powered remote monitoring terminals.

(3) Standby Mode

Mechanism Cuts power to the 1.8V domain, with only backup registers and RTC maintaining power, resulting in data loss, and the program starts from the beginning upon wake-up.

Wake-up Method Rising edge on the WKUP pin, RTC alarm, NRST reset, etc.

Application Scenario Devices with ultra-low power requirements that do not need to save state, such as remote controls.

4. Power Monitoring and Protection

Programmable Voltage Detector (PVD) Monitors VDD voltage in real-time, triggering an interrupt to execute emergency tasks if it falls below a set threshold (e.g., 2.2V).

Automatic Wake-up Unit (AWU) Wakes up the device periodically through RTC, suitable for periodic tasks (e.g., collecting data once an hour).

5. Code Implementation Example

Entering Stop Mode (HAL Library)