Clock Design SolutionsIn complex FPGA designs, creating a clocking solution is a challenging task. Designers need to have a good grasp of the clock resources available in the target device and their limitations, understand the trade-offs between different design techniques, and possess a solid knowledge of a range of design practices. Incorrect designs or suboptimal clock solutions can lead to poor design performance in the best case, or random and hard-to-find errors in the worst case.The clock resources in an FPGA refer to the various clock-related resources in the target FPGA, such as clock types (local and global), frequency limitations, jitter characteristics of different clock managers, and the maximum number of clocks that can be used for a single clock domain.This article introduces each part of the clock design solutions and recommends some design methodologies.The internally generated clock is the output of combinational logic or registers, as shown in Figure 1.Clocks generated by combinational logic may have glitches, which can be misinterpreted as valid clock edges, leading to functional errors in the design. Therefore, do not use the output of combinational logic as a clock.Internally generated clocks use general routing resources. Consequently, the delay is longer compared to dedicated clock routing. The consequence is increased clock skew, making it more difficult to meet timing requirements. This issue is particularly prominent if a large amount of logic uses this internal clock. Public Account:OpenFPGAAs a general rule, try to avoid using internally generated clocks and use dedicated clock resources whenever possible.Except for some special circuits [such as double data rate (DDR) data capture], data is usually captured on the rising or falling edge of the clock. The problem with using both edges arises because the clock duty cycle may not always be 50%, which can affect the normal operation of the circuit.It is recommended to use differential clocks at high frequencies. Frequencies above 100MHz are generally considered high frequency. The main advantage of differential clocks over single-ended clocks is common-mode noise suppression, thus providing better noise immunity. Differential clocks with PECL, LVPECL, and LVDS signal levels are preferred for high-speed logic.Xilinx FPGA provides several dedicated primitives for differential clocks: IBUFDS, IBUFGDS, IBUFGDS_DIFF, OBUFDS, and OBUFTDS (see Figure 2).Clock gating is a method in designs to control the clock input to registers and other synchronous elements using control signals. It can effectively reduce power consumption and is widely used in ASIC designs. However, in FPGA designs, gated clocks should be avoided as much as possible.It is not recommended to use clock signals as control, reset, or data inputs for general logic. Below is an example of such circuits.
module clock_schemes(input clk1,clk2,clk3,clk4,clk5,input data_in,output reg data_out1,data_out2,data_out3,data_out4,data_out5,data_out6);wire data_from_clock, reset_from_clock, control_from_clock;/ / Clock is used as data inputassign data_from_clock = clk1;always @(posedge clkl) data_out1 <= ~data_out1;always @(posedge clk2) data_out2 <= ~data_out2 & data_from_clock;/ / Clock is used as reset inputassign reset_from_clock = clk3;always @(posedge clk3) data_out3 <= ~data_out2;always @(posedge clk4, posedge reset_from_clock) if (reset_from_clock) data_out4 <= 0; else data_out4 <= data_in;/ / Clock is used as controlassign control_from_clock = clk5;always @(posedge clk5) data_out5 <= ~data_out5;always @(*) data_out6 = control_from_clock ? data_in : data_out6;endmodule // clock schemes
Many peripherals interfacing with FPGA use a source-synchronous clock that is the same as the data. If the interface operates at high speed, it may be necessary to calibrate the clock edge to capture data in the middle of the data window. To achieve dynamic calibration, Xilinx MMCM primitives provide a dynamic reconfiguration port (DRP), allowing programmable phase shifts of the clock. Figure 3 illustrates how the clock from MMCM is shifted so that the rising edge of the clock samples data in the middle of the window.When the same logic has clocks from different clock sources, it is necessary to multiplex these clock sources in the design (see Figure 4). An example is an Ethernet MAC that uses 2.5MHz, 25MHz, or 125MHz clocks, with the choice of clock depending on the negotiated speed of 10Mbps, 100Mbps, or 1Gbps.Another example is a built-in self-test (BIST) circuit that uses different clock signals from the same clock source during normal operation. Public Account:OpenFPGAIt is recommended to use dedicated clock resources for clock multiplexing, ensuring that input and output clocks use dedicated clock lines rather than general logic. The frequencies of the clocks involved in multiplexing may not be related to each other. Multiplexers implemented with combinational logic can generate glitches on the clock line during switching, which can jeopardize the entire system. These glitches can be interpreted as valid clock edges by some registers while ignored by others.Xilinx provides the BUFGMUX primitive that can multiplex between two global clock sources. It also ensures that there are no glitches when switching the input clock. Clock multiplexing requires detailed timing constraints on all clock paths from input to output in the multiplexer.One method to detect clock absence is to oversample it using another faster clock; the downside is that there may not be a suitable high-speed clock available. Another method is to use the locked output of the Xilinx MMCM primitive, as shown in Figure 5.
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