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As a PCB design engineer, it is essential to possess knowledge about high-speed signals. High-speed signals are typically found in various parallel buses and serial buses. Understanding what a bus is will help you determine its speed and start routing.
Bus
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Parallel Bus
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Serial Bus
Routing Requirements
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(1) It is recommended to route the bus on inner layers, increasing the distance from other routes as much as possible.
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(2) Unless otherwise specified, ensure a single line design impedance of 50 ohms and a differential design impedance of 100 ohms.
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(3) It is recommended to keep the routing of the same group of buses approximately equal in length and follow a certain timing relationship with the clock line, referring to timing analysis to control routing length.
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(4) It is advisable to place the I/O power or GND reference plane as close as possible to the bus group to ensure the integrity of the reference plane.
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(5) For buses with a rise time of less than 1ns, a complete reference plane is required, and they must not cross splits.
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(6) It is recommended to refer to the routing requirements of the clock for lower address buses.
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(7) The spacing of serpentine routing should not be less than three times the line width.
High-Speed Serial Bus Routing Requirements
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(1) High-speed serial buses need to consider routing losses, determining line width and length.
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(2) It is generally recommended that line width not be less than 5mil, and routing should be kept as short as possible.
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(3) Except for fanout vias, high-speed serial buses should avoid layer changes as much as possible.
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(4) For plug pins involved in serial buses with rates above 3.125Gbps, optimize the pads to reduce impedance discontinuities.
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(5) When changing layers for high-speed serial bus routing, choose the routing layer with minimal via stubs. For signals going to the connector, if routing space is limited, prioritize assigning the layer with shorter via stubs to the transmitter.
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(6) When the rate reaches 3.125Gbps or above, ground holes should be placed next to signal vias, and AC coupling capacitors must be specially treated for pads.
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(7) If high-speed signal vias are treated with back drilling, consider the reduced current-carrying capacity of the power ground plane and the increased inductance of the filtering loop due to the narrower current bottleneck.
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(8) High-speed signals should avoid crossing split lines in plane layers, ensuring a horizontal spacing of 3W between the edges of signal lines and split lines.
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(9) High-speed signals in both transmission directions must not cross each other.
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