Detailed Guide on MPU Configuration and Usage for S32K1xx Series MCU in Embedded System Software Development

Summary

Introduction

1. Introduction to the MPU Module Functions of S32K1xx Series MCU

1.1 Logical Bus Master ID and Slave Allocation Managed by the MPU Module of S32K1xx Series MCU

1.2 Functional Characteristics of the MPU of S32K1xx Series MCU

2. Introduction to MPU Module Registers

2.1 Control and Error Status Register (CESR)

2.2 Error Address Registers (EAR0 – EAR4)

2.3 Error Detail Registers (EDR0 – EDR4)

2.5 Reset Values of Region Descriptor Configuration Word Registers and Default Configuration of MPU

3. Detailed Functionality of the MPU Module of S32K1xx Series MCU

3.1 Hit Determination

3.2 Privilege Violation Determination

4. SDK Usage and Configuration Considerations for the MPU of S32K1xx Series MCU

4.1 Introduction to MPU Configuration Components in S32K SDK

4.2 Tips for Using MPU Configuration Components in S32K SDK and Configuration Considerations

Conclusion

Introduction

With the increasing complexity and functionality of embedded systems, MCU-based embedded systems are increasingly using real-time operating systems (RTOS) to manage multitasking. These systems must provide a mechanism to ensure that running tasks do not disrupt the operation of other tasks, preventing illegal access to system resources and other tasks. Embedded systems have dedicated hardware to detect and limit access to system resources, ensuring ownership of system resources. Tasks must adhere to a set of rules defined by the operating environment and maintained by hardware, granting special privileges for monitoring and controlling resource access at the hardware level. A protected system actively prevents one task from using the resources of another task. Therefore, using hardware to actively monitor the system can provide better protection than coordinated software solutions.

MPU—Memory Protection Unit, is a commonly used hardware protection system resource in MCUs based on ARM Cortex M series cores, providing memory area protection functionality.

This article takes NXP’s S32K1xx series automotive-grade MCU MPU as an example to discuss the typical working principles and configuration methods of MPUs, as well as specific engineering practices and considerations for MPU configuration.

1. Introduction to the MPU Module Functions of S32K1xx Series MCU

In the S32K1xx series MCU, as one of the security mechanisms of the MCU, the MPU module does not use the official ARM version that only supports CPU core memory access permission management, but instead uses NXP’s own system MPU IP to control/protect the access permissions of the Crossbar bus matrix master to the memory-mapped address areas. It can provide memory protection functionality at the Crossbar bus interconnection matrix level, allowing configuration of different access permissions for each Crossbar Master (CPU core, debugger interface, DMA, and ENET) to each protected memory area (as Crossbar slave).

Functional block diagram of S32K14x series MCU:

Functional block diagram of S32K11x series MCU:

1.1 Logical Bus Master ID and Slave Allocation Managed by the MPU Module of S32K1xx Series MCU

The logical bus Master ID allocation managed by the MPU module of the S32K1xx series MCU is shown in the following table, where only the CPU Core and Debugger controller have PID (Process ID) and have all access type permissions:

The logical bus Slave port allocation managed by the MPU module of the S32K1xx series MCU is shown in the following table (where S32K14x series MCU has a CM4F core, and the access to SRAM occupies 3 Slave ports, where the internal Core Code bus and System bus access to SRAM, although not passing through the Crossbar bus matrix, is still monitored and managed by the MPU module. Additionally, there is a Crossbar bus matrix slave port allocated to the only QSPI module of S32K148 for AHB mode data access; while S32K11x series MCU only has two slave ports for Flash and SRAM access):

1.2 Functional Characteristics of the MPU of S32K1xx Series MCU

The MPU of S32K1xx series MCU has the following functional characteristics:

• 16 programmable 128-bit region descriptors, each composed of 4 32-bit words (0~3) for access;

• Each region descriptor defines a 32-byte aligned memory-mapped space

• Region sizes range from a minimum of 32 bytes to a maximum of 4GB;

• Two access control permissions can be defined within a single region descriptor word

• Master0~3: Attributes for read (R), write (W), and execute (X) in both administrator and user modes;

• Master4~7: Read and write attributes

• Hardware-assisted maintenance of descriptor validity bits minimizes memory access consistency issues;

• Provides an alternate programming model for access control permission words;

• Allows prioritization of access denial capabilities for overlapping region descriptors;

• If the bus master access does not hit any memory-mapped region or violates all access permissions of the memory-mapped regions, the MPU can detect access protection errors. If an access error is detected, it will terminate the current bus master access and return an error response, while the MPU will prohibit access to the target slave device during the current bus cycle;

• Each slave port provides error registers to capture the address, attributes, and other information of the last failed access;

• Provides a global MPU enable/disable control bit;

2. Introduction to MPU Module Registers

The MPU module of S32K1xx series MCU consists of several pairs of access evaluation macros (Access Evaluation Macro) and region descriptors (Region Descriptor) in a two-dimensional connection matrix, whose simplified functional block diagram is as follows:

The MPU module of the S32K1xx series MCU is configured through region descriptors, and the number of region descriptors available for each part number is shown in the following table (where S32K148 has 16 region descriptors and 5 slave ports—adding a QSPI access port):

Tips: Since the reset value of the CESR register’s least significant bit (VLD—MPU global enable) is 1, the MPU module is enabled by default after each MCU reset;

All MPU region descriptor configurations are implemented through registers. Next, I will provide a detailed introduction to the configuration registers of the MPU module.

2.1 Control and Error Status Register (CESR)

The highest 5 bits of this register—SPERR0~4 are write-1-clear (W1C) error status registers corresponding to whether access errors exist for the 5 Crossbar bus matrix slave ports managed by the MPU module;

NSP and NRGD are read-only bits used to indicate the number of Slave ports managed by the MPU module of this MCU and the number of region descriptors owned, which vary by part number;

The least significant bit—VLD is the global enable control bit for the MPU. If VLD=0, the MPU is off, allowing all Crossbar bus matrix master accesses. After reset, this bit is 1, so the MPU is enabled by default:

2.2 Error Address Registers (EAR0 – EAR4)

When the MPU module detects an access violation error when the current Master accesses Slave port n, it captures the target access address and stores it in the corresponding error address register (EARn), setting CESR[SPERRn] to 1. This register is read-only, and if multiple errors occur, it only retains the access address of the last error:

2.3 Error Detail Registers (EDR0 – EDR4)

This read-only register group provides detailed information about the access error that occurred when accessing Slave port n, mainly including:

EACD[15:0]: Each bit indicates whether an access error exists for a region descriptor:

• ① If no bits in EACD[15:0] are set to 1, it indicates that the access did not hit any region descriptors;

• ② If only one bit in EACD[15:0] is set to 1, it indicates that the current error is caused by a single non-overlapping region descriptor;

• ③ If 2 or more bits in EACD[15:0] are set to 1, it indicates that the current error is caused by overlapping region descriptors;

EPID: Records the Master processing ID (PID) that caused the error;

EMN: Records the Master ID that caused the error;

EATTR: Records the error attributes (Attributes). CPU core’s User/Supervisor mode instruction (Instruction) access/data (Data) access;

ERW: Records the error access type—read (0) or write (1);

2.4 Region Descriptor Configuration Word Registers (RGD0_WORDx – RGD15_WORDx)

Where configuration word 0 register (RGDn_WORD0) defines the starting address applicable to the access rules defined by this region descriptor, and configuration word 1 register (RGDn_WORD1) defines the ending address applicable to the access rules defined by this region descriptor:

① Configuration word 0 register (RGDn_WORD0) defines

② Configuration word 1 register (RGDn_WORD1) defines

③ Configuration word 2 register (RGDn_WORD2) defines the read/write permission for bus Master 4~7 (M4RE~M7RE, set to 1 to allow read; M4WE~M7WE, set to 1 to allow write), access control for Master 0~3 in Supervisor mode (M0SM~M3SM) and User mode (M0UM~M3UM), and whether the processing ID (PID) check for Master 0~1 is enabled (M0PE~M1PE):

④ Configuration word 3 register (RGDn_WORD3) defines whether the region descriptor enables the MPU to check the PID for the bus master (PID specifies the required master processing ID, PIDMASK[7:0]—each bit corresponds to a bus master, set to 1 to mask the PID check for that bus master) and whether the region descriptor is valid (VLD);

2.5 Reset Values of Region Descriptor Configuration Word Registers and Default Configuration of MPU

According to the reference manual of the S32K1xx series MCU—S32K-RM.pdf, the reset values of the MPU region descriptor configuration word registers are as follows:

Region Descriptor	Configuration Register	Reset Value	Meaning
0	RGD0_WORD0	0x0000_0000	Region starting address is 0x0000_0000
RGD0_WORD1	0xFFFF_FFFF	Region ending address is 0xFFFF_FFFF
RGD0_WORD2	0x0061_F7DF	Allows Crossbar all bus Masters to access Slave in Supervisor and User modes and PID checks
RGD0_WORD3	0x0000_0001	Enables this region descriptor, meaning the access rules are valid
n=1~15(S32K148)/ 1~7(others)	RGDn_WORD0	0x0000_0000	Region starting address is 0x0000_0000
RGDn_WORD1	0x0000_001F	Region ending address is 0x0000_001F (not meaningful, reserved for alignment)
RGDn_WORD2	0x0000_0000	Prohibits all access
RGDn_WORD3	0x0000_0000	This descriptor is invalid

As mentioned in the previous section, it includes 32/64 32-bit registers, with 4 registers in a group divided into 8/16 groups, each configuring a region descriptor—i.e., an access rule for a Crossbar bus master and slave. Each region descriptor can be individually enabled (through the valid bit of configuration word 3 register (RGDn_WORD3[VLD])), in addition to a global enable control bit (CESR[LVD]).

Since after reset CESR[LVD]=1, the MPU of the S32K1xx series MCU is globally enabled by default, and region descriptor 0 is also enabled, so after MCU reset, the default configuration of MPU is to allow Crossbar all bus Masters to have access permissions in Supervisor and User modes and PID checks.

3. Detailed Functionality of the MPU Module of S32K1xx Series MCU

The access permission control logic of the MPU module is mainly completed by its access evaluation macro module (access evaluation macro), whose functional block diagram is as follows:

Every access by the Crossbar bus master will logically judge with all valid MPU region descriptor rules. This logical judgment process occurs in parallel simultaneously, and each logical judgment includes hit determination and privilege violation determination:

3.1 Hit Determination

RGDn_Word0[SRTADDR] specifies the starting address, RGDn_Word1[ENDADDR] specifies the ending address, RGDn_Word3[VLD] is the valid bit; if the address accessed by the current bus master addr[31:5] satisfies the following logical operation, it is called region hit (region_hit):

region_hit = ((addr[31:5] >= RGDn_Word0[SRTADDR]) & (addr[31:5] <= RGDn_Word1[ENDADDR])) & RGDn_Word3[VLD];

Tips: The MPU will ignore address access rules specified by descriptors where ENDADDR ≤ SRTADDR;

Meanwhile, the MPU will also check whether the optional processing ID (PID) configured by the descriptor’s PID and PIDMASK bits matches the PID of the currently initiating bus master. This process is called PID hit (pid_hit), and the specific check control logic is as follows (for bus masters without PID, the MPU defaults to PID hit success):

pid_hit = ~RGDn_Word2[MxPE] | ((current_pid | RGDn_Word3[PIDMASK]) == (RGDn_Word3[PID] | RGDn_Word3[PIDMASK]));

When both region hit (region_hit) and PID hit (pid_hit) succeed, this bus master access hit (hit) is successful;

3.2 Privilege Violation Determination

During the above region hit judgment, the MPU’s control logic simultaneously conducts privilege determination for the current access according to the access permissions defined by the descriptors, using Master control signals and supervisor/user mode signals to determine access permissions—read/write/executable (r/w/x) protection violation determination rules are as follows:

Based on the above evaluation results, for each bus slave port access monitoring, the MPU will execute a simple AND operation on the evaluation results of each independent access evaluation macro module, thereby generating bus access errors and protection errors, terminating bus access or allowing the current access:

① If the current access does not hit any region descriptor, a protection error will occur;

② If the current access hits a region descriptor, the region descriptor control signal will report protection violation and protection error signals;

③ If the current access hits multiple (including overlapping) region descriptors, all hit region descriptor control signals will report protection violation and protection error signals;

4. SDK Usage and Configuration Considerations for the MPU of S32K1xx Series MCU

Combining the theoretical introduction above, I will now introduce how to configure and use the S32K SDK to complete the MPU module configuration of the S32K1xx series MCU in S32DS for ARM IDE.

4.1 Introduction to MPU Configuration Components in S32K SDK

In the S32K SDK (RTM2.0 version), two components are provided to configure the MPU of S32K1xx series MCU:

mpu_pal: A peripheral abstraction layer MPU configuration component, further abstracted from the MPU peripheral driver layer component, suitable for different MCU platforms: for example, it can configure not only the S32K1xx series MCU but also the MPC57xx series MCU and S32R series MPU modules; configuration efficiency is slightly lower than the mpu component:

It only provides APIs for initialization, de-initialization, obtaining default region configuration, updating region descriptors, enabling region descriptors, and obtaining errors;

The corresponding configuration interface is as follows:

mpu: The MPU configuration component specifically for S32K1xx series MCU, belonging to the peripheral driver layer, only suitable for configuring the MCU module of S32K1xx series MCU, with poor generality and portability, but high configuration efficiency;

It provides APIs for initialization, de-initialization, setting region descriptor addresses, setting bus Master access permissions, obtaining detailed access error information, obtaining default region configuration, enabling region descriptors, etc.;

The corresponding configuration interface is as follows:

Both mpu and mpu_pal have similar configuration interfaces, and through the Processor Expert GUI interface provided by S32DS IDE, it is very easy to configure the starting address, ending address, PID configuration, and specific access permissions for each region descriptor of the MPU. Below, I will introduce the configuration component of the mpu peripheral driver layer as an example:

In the User Configuration property, you can add user configurations. After selecting a user configuration, you can add several regions (region, corresponding to the MPU module’s region descriptor, so the maximum number of regions is the maximum number of region descriptors supported by the specific MCU part, S32K1xx and S32K142/4/6 are 8, S32K148 is 16), where you can configure the starting address (Start address), ending address (End address), and Master access rights configuration selection (Master access right):

In the Master access rights property, you can add several bus Master access rights configurations, and then select one to configure the specific access permissions of the bus Master (CPU core, Debugger, and DMA module) in Supervisor and User modes, as well as PID enable:

For API function parameter descriptions and usage of the above components, please refer to their help manual. In the S32DS IDE component browser window, select the SDK configuration component, then right-click -> select Doxygen Documentation to open its help manual:

4.2 Tips for Using MPU Configuration Components in S32K SDK and Configuration Considerations

The following specific application engineering practices provide several tips for using MPU configuration components in S32K SDK and configuration considerations, hoping to be helpful:

① If in User Configuration -> Region Configuration, Region enable has been checked (default checked), then after calling the MPU initialization function (MPU_DRV_Init()/MPU_Init), the access rules of this region descriptor will be valid. Otherwise, you need to call the MPU region enable function (MPU_DRV_EnableRegion()/MPU_EnableRegion) to enable it to take effect;

② In the SDK, by default, region descriptor 0 is enabled according to the reset values in the reference manual, meaning that the entire 4G address mapping space from 0x0000_0000 to 0xFFFF_FFFF is allowed for all types of access by running bus Masters. Importantly, in the SDK configuration, the enable control, starting address, ending address, and Master access right (mpu_pal1_AccessRightConfig0/mpu_AccessRightConfig0) configuration of Region 0 cannot be modified:

According to the overlapping characteristic of the MPU region descriptor access rules, you must configure its AccessRightConfig0 to not allow all types of access, and then set individual region addresses for different access permissions to take effect. Otherwise, all region descriptor rules configured through other Region configurations will not take effect:

③ When configuring the MasterAccessRightConfig selection for Region, the address space where the application code runs (Flash/RAM) cannot be configured to prohibit read (r) and execute (x)—i.e., “—“/”-w-“/”-wx”/”rw-“. Otherwise, after enabling the MPU configuration, the CPU will reset because it cannot continue executing code or access interrupt vectors to enter CPU core exceptions;

④ The MPU is a system-level security module that provides an interrupt handling mechanism at the peripheral module level. Once a region descriptor access violation occurs, it triggers a system exception in the CPU core. Specifically, in the S32K1xx series MCU, it will enter the hardware error exception (HardFault) of the ARM Cortex M0+/M4F. In this case, when calling the API to obtain access error detailed information—MPU_DRV_GetDetailErrorAccessInfo() to read the relevant error address and status register values in the MPU, as shown in the test code I wrote, prohibiting the CPU core from writing (w) access permissions to 0x2000_0000~0x2000_1000 4KB SRAM, then writing values to the global variables in it resulted in the following exception, entering HardFault_Handler():

Through Region1, configure region descriptor 1 to control 0x2000_0000~0x2000_1000 of 4KB SRAM, selecting memProtect1_AccessRightConfig1 as its Master access right configuration:

In the memProtect1_AccessRightConfig1 configuration, set the access permission of the CPU core to read-only (“r–“), prohibiting write operations:

⑤ The default HardFault exception handling function (ISR) for the S32DS S32K1xx series MCU application project uses the same default ISR function—DefaultISR, which is implemented as a dead loop by a branch assembly instruction (b—branch):

.align 1

.thumb_func

.weak DefaultISR

.type DefaultISR, %function

DefaultISR:

b DefaultISR

.size DefaultISR, . – DefaultISR

To identify HardFault exceptions, users need to define their own exception handling function. Since the startup assembly file uses the .weak assembly directive to define HardFault_Handler, it allows users to overload it.

Thus, adding a user-defined HardFault_Handler is very simple—just redefine HardFault_Handler in any .c file:

Conclusion

This article provides a detailed introduction to the working principles and configuration methods of the MPU module of the S32K1xx series MCU. Through the configuration of region descriptors, it achieves access permission control for specific address-mapped system resources (such as RAM and NVM storage and the reading and writing of peripheral control and configuration registers, as well as executable code permissions), ensuring the secure and efficient operation of multitasking system software.

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