Welcome FPGA engineers to join the official WeChat technical group
Clickblue wordsFollow us at FPGA Home – the best and largest FPGA pure engineer community in China
A
ASIC (Application-Specific Integrated Circuit). A piece of custom-designed hardware in a chip.
address bus A set of electrical lines connected to the processor and all of the peripherals with which it communicates.
application software Describes software modules specific to a particular embedded project.
assembler A software development tool that translates human-readable assembly language programs into machine-language instructions.
assembly language A human-readable form of a processor’s instruction set.
B
BSP (Board Support Package).
binary semaphore A type of semaphore with just two states.
board support package Part of a software package that is processor or platform-dependent.
bond-out processor A special version of a processor that has some of the internal signals brought out to external pins.
Breakpoint A location in a program at which execution is to be stopped and control of the processor switched to the debugger.
C
CISC (Complex Instruction Set Computer).
CPU (Central Processing Unit).
Compiler A software development tool that translates high-level language programs into machine-language instructions.
context The current state of the processor’s registers and flags.
context switch The process of switching from one task to another in a multitasking operating system.
counting semaphore A type of semaphore that is used to track multiple resources of the same type.
critical section A block of code that must be executed in sequence and without interruption to guarantee correct operation of the software.
cross-compiler A compiler that runs on a different platform than the one for which it produces object code.
D
DMA (Direct Memory Access).
DRAM (Dynamic Random-Access Memory).
Data bus A set of electrical lines connected to the processor and all of the peripherals with which it communicates.
Deadline The time at which a particular set of computations must be completed.
Deadlock An unwanted software situation in which an entire set of tasks is blocked.
debug monitor A piece of embedded software that has been designed specifically for use as a debugging tool.
Debugger A software development tool used to test and debug embedded software.
device driver A software module that hides the details of a particular peripheral and provides a high-level programming interface to it.
device programmer A tool for programming non-volatile memories and other electrically-programmable devices.
digital signal processor A device that is similar to a microprocessor, except that the internal CPU has been optimized for use in applications involving discrete-time signal processing.
E
EEPROM (Electrically Erasable, Programmable Read-Only Memory).
EPROM (Erasable, Programmable Read-Only Memory).
embedded system A combination of computer hardware and software, and perhaps additional mechanical or other parts, designed to perform a dedicated function.
Emulator Short for In-Circuit Emulator (ICE).
Executable A file containing object code that is ready for execution on the target.
F
Firmware Embedded software that is stored as object code within a ROM.
flash memory A RAM-ROM hybrid that can be erased and rewritten under software control.
G
general-purpose computer A combination of computer hardware and software that serves as a general-purpose computing platform.
H
HLL See high-level language.
Heap An area of memory that is used for dynamic memory allocation.
high-level language A language, such as C or C++, that is processor-independent.
Host A general-purpose computer that communicates with the target via a serial port or network connection.
I
ICE In-Circuit Emulator.
I/O (Input/Output).
I/O device A piece of hardware that interfaces between the processor and the outside world.
I/O map A table or diagram containing the name and address range of each peripheral addressable by the processor within the I/O space.
I/O space A special memory region provided by some processors and generally reserved for the attachment of I/O devices.
ISR (Interrupt Service Routine).
Interrupt An asynchronous electrical signal from a peripheral to the processor.
interrupt latency The amount of time between the assertion of an interrupt and the start of the associated interrupt service routine.
interrupt service routine A piece of software executed in response to a particular interrupt.
interrupt type A unique number associated with each interrupt.
interrupt vector The address of an interrupt service routine.
interrupt vector table A table containing interrupt vectors and indexed by interrupt type.
intertask communication A mechanism used by tasks and interrupt service routines to share information and synchronize their access to shared resources.
K
Kernel An essential part of any multitasking operating system.
L
Linker A software development tool that accepts one or more object files as input and outputs a relocatable program.
Locator A software development tool that assigns physical addresses to the relocatable program produced by the linker.
logic analyzer A hardware debugging tool that can be used to capture the logic levels of dozens of electrical signals in real-time.
M
memory map A table or diagram containing the name and address range of each peripheral addressable by the processor within the memory space.
memory-mapped I/O An increasingly common hardware design methodology in which I/O devices are placed into the memory space rather than the I/O space.
memory space A processor’s standard address space.
Microcontroller A microcontroller is very similar to a microprocessor.
Microprocessor A piece of silicon containing a general-purpose CPU.
Monitor In the context of this book, a debug monitor.
Multiprocessing The use of more than one processor in a single computer system.
Multitasking The execution of multiple software routines in pseudo-parallel.
Mutex A data structure for mutual exclusion.
mutual exclusion A guarantee of exclusive access to a shared resource.
N
NVRAM Non-Volatile Random-Access Memory.
O
OTP See one-time programmable.
object code A set of processor-readable opcodes and data.
object file A file containing object code.
one-time programmable Any programmable device that can be programmed just once by the end user.
opcode A sequence of bits that is recognized by the processor as one of the instructions in its instruction set.
operating system A piece of software that makes multitasking possible.
Oscilloscope A hardware debugging tool that allows you to view the voltage on one or more electrical lines.
P
PROM Programmable Read-Only Memory.
parallel processing The ability to apply two or more processors to a single computation.
Peripheral A piece of hardware other than the processor.
physical address The actual address that is placed on the address bus when accessing a memory location or register.
Preemptive A scheduler is said to be preemptive if it allows the running task to be suspended when a higher-priority task becomes ready.
Polling A method of interfacing with hardware that involves repeatedly reading a status register.
Priority The relative importance of one task compared to another.
priority inversion An unwanted software situation in which a high-priority task is delayed.
Process A word that is often confused with task or thread.
Processor A generic term that does not distinction between microprocessor, microcontroller, and digital signal processor.
processor family A set of related processors.
processor-independent A piece of software that is independent of the processor on which it will be run.
processor-specific A piece of software that is highly dependent on the processor on which it will be run.
Profiler A software development tool that collects and reports execution statistics for your programs.
program counter See instruction pointer.
R
RAM Random-Access Memory.
RISC (Reduced Instruction Set Computer).
ROM Read-Only Memory.
ROM emulator A debugging tool that takes the place of the ROM on your target board.
ROM monitor See debug monitor.
RTOS Real-Time Operating System.
race condition A situation in which the outcome of a program may be affected by the exact order in which the instructions are executed.
real-time system Any computer system, embedded or otherwise, that has deadlines.
Recursive Said of software that calls itself.
Reentrant Said of software that can be executed multiple times simultaneously.
Register A memory location that is part of a processor or an I/O device.
Relocatable A file containing object code that is almost ready for execution on the target.
reset address The address from which the first instruction will be fetched after the processor is powered on or reset.
reset code A small piece of code that is placed at the reset address.
reset vector See reset address.
S
SRAM Static Random-Access Memory.
Scheduler The part of an operating system that decides which task to run next.
Semaphore A data structure that is used for intertask synchronization.
Simulator A debugging tool that runs on the host and pretends to be the target processor.
software interrupt An interruption of a program that is initiated by a software instruction.
Stack An area of memory that contains a last-in-first-out queue of storage for parameters, automatic variables, return addresses, and other information.
stack frame An area of the stack associated with a particular function call.
startup code A piece of assembly language code that prepares the way for software written in a high-level language.
T
Target Another name for the embedded system.
Task The central abstraction of an operating system.
Thread Another name for a task.
Tracepoint Like a breakpoint except that a counter is incremented rather than stopping the program.
Trap An interruption of a program that is triggered by the processor’s own internal hardware.
V
volatile A value that may change without the intervention of software.
W
watchdog timer A hardware timer that is periodically reset by software.
Welcome communication engineers and FPGA engineers to follow the public account
The largest FPGA WeChat technical group in the country
We welcome everyone to join the national FPGA WeChat technical group, which has tens of thousands of engineers, a group of engineers who love technology. Here, FPGA engineers help each other and share with each other, creating a strong technical atmosphere! Hurry up and call your friends to join!!
Press and hold to join the national FPGA technical group
FPGA Home Component City
Advantageous component services, please scan the code to contact the group owner: Jin Juan Email: [email protected] Welcome to recommend to procurement
ACTEL, AD part of advantageous ordering (operating the full series):
XILINX, ALTERA advantageous stock or ordering (operating the full series):
(The above components are part of the models, for more models please consult the group owner Jin Juan)
Service concept: FPGA Home component self-operated city, aimed at facilitating engineers to quickly and conveniently purchase components. After years of sincere service, our customer service covers large listed companies, military research units, and small and medium enterprises. Our biggest advantage is to emphasize the service-first concept and achieve fast delivery and favorable prices!
Directly-operated brands: Xilinx ALTERA ADI TI NXP ST E2V, Micron and other hundreds of component brands, especially good at components subject to US embargo against China. We welcome engineer friends to recommend us to procurement or consult us personally! We will continue to provide the best service in the industry!
Official thanks to the brands of the FPGA technical group: Xilinx, Intel (Altera), Microsemi (Actel), Lattice, Vantis, Quicklogic, Lucent, etc.