Last week, ST announced that the new STM32 will soon adopt 18nm FD-SOI process embedded phase change memory (ePCM), and will start providing samples to some customers in the second half of 2024. This means that ST is the first to break the 20nm barrier for MCUs.

Regarding the process, many engineers have questions: Why are mobile chip processes at 3nm/2nm, while MCUs rarely upgrade their processes for performance? In fact, MCUs also need to upgrade their performance through process improvements, but first, they need to change the storage technology.

Fu Bin | Author

Electronic Engineering World (ID: EEworldbbs) | Produced

MCU processes are locked by eFlash

We cannot blame the MCU for not trying; we can only say that eFlash (embedded flash memory) technology has dragged down the MCU.

Many people have noticed that in recent years, MCUs have been lingering around 40nm. In fact, the non-volatile memory (eNVM) for MCUs has transitioned from EPROM/OTP to eFlash, which has been over twenty years ago.

In the 1990s, with programmability, non-volatility, and on-chip embedding, eFlash opened the “eFlash innovation” era in the MCU industry, which was worth billions of dollars at the time. Starting from the 0.8-micron technology node in 1991, eFlash technology has combined with standard CMOS logic technology, allowing MCUs to reach a product level of 28nm as early as 2015.

In 2016, Renesas developed the world’s first separated gate metal-oxide-nitride-oxide-silicon (SG-MONOS) flash memory cell, which targeted on-chip flash MCUs at 16nm to 14nm and above. However, now, this technology serves more Renesas’s 40nm MCUs.

Subsequently, technologies such as 16nm FinFET and FD-SOI have gradually made it lag behind the pace of the times. It can be said that eFlash, as an old soldier on the MCU chip, has developed several generations of products using technologies such as floating gate, SONOS, or SG-MONOS, but when faced with more complex demands, including higher performance-to-power ratios, higher storage densities, and digital circuit densities, it is also “getting old”.

The memory industry generally believes that the 28nm/22nm silicon lithography node will be the last economically efficient technology node for eFlash.

This is not due to scalability limitations, but is a result of cost and process considerations:

First, manufacturing eFlash at 28nm and below requires 9 to 12 layers or even more masks, while eFlash above 40nm requires at least 4 layers of masks. In comparison, new storage technologies like eMRAM only require 3 additional masks. It should be noted that MCUs have a total of four to five dozen layers, and the cost of more than a dozen layers is clearly incompatible with the MCU. Therefore, manufacturing eFlash below 28nm is not cost-effective, let alone putting it into MCUs that pursue extreme cost performance.

Second, higher eFlash process nodes will bring reliability issues. As the device scale exceeds 40nm, the reliability of eFlash systems is limited not only by the eFlash memory cells but also by peripheral transistors and metal interconnects. As the oxide film between the transistor devices and metal interconnects becomes thinner, the transient dielectric breakdown (TDDB) lifetime decreases significantly, posing enormous challenges for advanced eFlash designs. It is worth noting that eFlash occupies half of the MCU market precisely because of its strong reliability, which effectively eliminates its biggest advantage.

Third, it is difficult to integrate with advanced logic processes. For example, high-k metal gates, FD-SOI, and FinFET will impact the compatibility of the eFlash structure with CMOS, while new storage technologies such as MRAM and RRAM are hardly affected by the lower layer CMOS structures. Furthermore, technologies such as SONOS, nano-dot, and thin floating gate structures have advantages in nodes above 28nm.

In addition to improving the process, eFlash itself has also turned past advantages into problems when facing high computing power. For instance, eFlash has always been a conventional and primary source of high-density, on-chip non-volatile memory (NVM), but for small battery-powered applications, eFlash consumes too much of the system’s power budget. Moreover, it only supports page/block-level erasure and cannot perform byte writes, making it an expensive high-power solution. Additionally, in automotive applications, the rewritable cycles of eFlash integrated into onboard MCUs are too few, and with each write and erase cycle, the tunneling oxide in the floating gate NOR cells degrades, leading to increased leakage and accelerated aging of eFlash.

Recently, few institutions have studied eFlash, as the technology of eFlash products has nearly stagnated, with major participants including TSMC (40nm), UMC (28nm), Samsung (45nm), as well as IDMs like STMicroelectronics and Infineon. While most manufacturers have tried 28nm/22nm and higher processes to some extent, it is almost impossible to use them in MCUs.

New Storage Technologies Break the 28nm Wall

In the past, even eFlash at 40nm or 90nm was sufficient for MCU use.

As market demands become increasingly complex, MCUs are gradually developing towards higher frequencies above 200MHz, low power consumption, and large capacity storage. Coupled with the demand for heterogeneous multi-core, most devices on the chip also need to be pushed below 28nm, making the process limitations of eFlash more apparent.

From the perspective of performance and capacity trends of on-chip flash memory in automotive MCUs, the overall performance requirements for MCUs have increased by about 20 times over the past decade, growing at a rate of 35% per year. This is driven by architectural evolution, such as the use of high-speed cache memory and the implementation of multi-core CPUs, supporting the speed improvement of eFlash. Reliability design for device expansion, etc. Meanwhile, on-chip ROM capacity has been growing at a rate of 23% per year.

Therefore, manufacturers are actively seeking solutions, which is new storage technologies—potential technologies include eMRAM, eRRAM (eReRAM), ePCM, and eFeRAM. These technologies can significantly improve MCU performance and reduce overall power consumption.

Of course, this does not mean that eFlash is useless; it can only be said that eFlash has matured enough, and in the future, MCUs with eFlash and those with new storage will be two completely different tracks.

Currently, there are three types of new storage technologies that have begun to be used in MCUs—RRAM (Resistive RAM), MRAM/STT-MRAM (Magnetic RAM), and PCM (PCRAM, Phase Change Memory).

Of course, to be integrated into MCUs, they have all added an “e” (Embedded), namely eRRAM, eMRAM, ePCM.

First is RRAM (Resistive RAM), where Infineon is the largest player on this route. Infineon collaborates with TSMC for 28nm eRRAM.

Second is MRAM/STT-MRAM (Magnetic RAM), with Renesas and NXP being the main promoters. NXP collaborates with TSMC for 16nm FinFET eMRAM, while Renesas has developed 22nm eSTT-MRAM.

Third is PCM (PCRAM, Phase Change Memory), with STMicroelectronics being the main promoter. STMicroelectronics previously collaborated with Samsung for 28nm FD-SOI ePCM and has recently upgraded to 18nm FD-SOI ePCM.

From the layout of the above different players, it can be seen that the processes have broken through 28nm, primarily targeting the automotive market. Moreover, the theoretical process nodes of the aforementioned technologies can reach 5nm. Not only that, replacing eFlash has not only advanced the nodes further but has also brought more processes, including FD-SOI and FinFET.

Unavoidable Generation Gap

Although the MCU processes have gradually caught up with the pace of the times, will it constantly pursue very advanced processes? Probably not.

In fact, historically, the memory embedded in MCUs has always had a generational gap with the most advanced lithography processes. According to engineers, the reasons are multifaceted.

First, the mass production cost of advanced processes is high. The market determines demand, demand drives the market, and the industry rarely uses expensive MCUs for products. The price and volume of MCUs also find it difficult to compete for advanced processes, as high-value chips like mobile phones and graphics cards are the first users of advanced processes. For example, if a motorhome sells only a few units a year, the development of a new model will be relatively slow.

Second, the urgent need for the MCU to switch generations is not that high. After all, even now, 90nm or 40nm can meet most needs. The 18nm FD-SOI ePCM MCU and 28nm eRRAM MCU mentioned above mainly address new demands in the automotive market. Thus, the MCU field has always leaned more towards internal renovations rather than completely renovating the entire house; only when market demand reaches a certain scale will it take a new step.

Third, compared to MCUs, there are many alternative solutions. Sometimes, people have already started to choose more cost-effective embedded products or SoCs, such as the popular Allwinner T113. Even more so, some may follow Intel’s approach to Ultra processors, packaging IO, processors, RAM, ROM, and various small dies together.

In summary, having money can lead to the creation of more advanced products, and the first to change is the automotive field. Of course, I believe that in the future, with the expansion of AI demand and changes in downstream smart devices, the cost and technological maturity of new storage will continue to advance, and eventually, new storage will gradually expand into the entire MCU field. By then, the entire MCU process will also advance further.

References

[1] ST: https://newsroom.st.com/media-center/press-item.html/c3244.html

[2] Synopsys: https://www.synopsys.com/zh-cn/designware-ip/technical-bulletin/future-nvm-memories.html

[3] Synopsys: https://www.synopsys.com/zh-cn/blogs/chip-design/what-is-emram.html

[4] Global Foundries: https://mp.weixin.qq.com/s/GKkHdm3iTJZkOPvxoSLOMA

[5] Zhihu: https://www.zhihu.com/question/648650264

[6] Semi Businessweek: https://mp.weixin.qq.com/s/vFv3Q26WEqgaOwOWNtu5IQ

[7] Flash Memory Summit: https://www.flashmemorysummit.com/Proceedings2019/08-06-Tuesday/20190806_CHNA-101-1_Yang.pdf

[8] Y. Taito et al., “7.3 A 28nm embedded SG-MONOS flash macro for automotive achieving 200MHz read operation and 2.0MB/S write throughput at Ti, of 170°C,” 2015 IEEE International Solid-State Circuits Conference – (ISSCC) Digest of Technical Papers, San Francisco, CA, USA, 2015, pp. 1-3, doi: 10.1109/ISSCC.2015.7062961.

[9] Hidaka, Hideto, ed. Embedded flash memory for embedded systems: technology, design for sub-systems, and innovations. Springer, 2017.

[10] Any Silicon: https://anysilicon.com/mram-a-promise-beyond-eflash/

[11] Astroys: https://mp.weixin.qq.com/s/CaJt62nooMY8ejvIzwXt5Q

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