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【Topic】: Basic Structure of FPGA
【Author】: LinCoding
【Date】: 2016.12.13
【Statement】: Please indicate the source for reprints and citations
Summary from “Altera FPGA/CPLD Design Basics, Second Edition”.
Basic Structure of FPGA:
The basic components of FPGA include: programmable I/O units, basic programmable logic units, embedded RAM blocks, abundant routing resources, underlying embedded functional units, and embedded dedicated hard cores.
1. Programmable I/O Units:
Programmable I/O units can adapt to different electrical standards and physical characteristics through software.
2. Basic Programmable Logic Units:
The basic programmable logic unit is the main body of the FPGA’s programmable logic. FPGAs are generally based on SRAM technology. The basic programmable logic unit is mostly composed of lookup tables (LUTs) and registers. The internal LUTs of FPGAs are generally 4-input, mainly performing pure combinational logic functions. The internal register structure is quite flexible and can be configured as flip-flops (FF) with synchronous or asynchronous reset or set, or clock enable, and can also be configured as latches. FPGAs generally rely on registers to complete synchronous sequential logic design.
A classic configuration of the basic programmable logic unit is one register and one LUT. However, there are certain differences in the internal structure of registers and LUTs from different vendors, and the combination modes of registers and LUTs also vary.
(1) Altera’s programmable logic units are usually referred to as LE (Logic Element), consisting of one register and one LUT. Most of Altera’s FPGAs combine 10 LEs to form larger logic functional units—Logic Array Blocks (LABs), which include not only LEs but also carry chains between LEs, LAB control signals, local interconnect resources, LUT cascading chains, register cascading chains, and other wiring and control resources.
(2) Xilinx’s programmable logic units are called Slice, composed of two parts. Each part consists of one register and one LUT, referred to as LC (Logic Cell), with some shared logic between the two LCs. This allows for coordination and cascading between LCs.
(3) Lattice’s programmable logic units are called PFU (Programmable Function Unit), consisting of 8 LUTs and 8-9 registers.
Generally, the number of registers and LUTs used in a device is a more accurate measure of the device’s scale.
3. Embedded RAM Blocks:
The embedded RAM blocks in FPGAs can be flexibly configured as single-port RAM (SPRAM), dual-port RAM (DPRAM), pseudo dual-port RAM (Pseudo DPRAM), CAM (Content Addressable Memory), FIFO (First Input First Output), and other common memory structures.
FPGAs do not have dedicated ROM hardware resources; the idea of implementing ROM is to assign initial values to RAM and maintain those initial values.
CAM, or content-addressable memory, includes embedded comparison logic in each storage unit. The data written to CAM will be compared with every piece of data stored internally and return the addresses of all internal data that match the port data.
In short, RAM is a storage unit that reads and writes data based on addresses, while CAM returns internal addresses that match port data.
The implementation of RAM, ROM, CAM, FIFO, and other storage structures within FPGAs is based on embedded RAM blocks, and corresponding glue logic is automatically generated according to the requirements to complete control logic such as address and chip selection.
Common RAM block sizes for Xilinx are 4Kbit and 18Kbit, while Lattice commonly uses 9Kbit. Altera’s RAM blocks are the most flexible, with some high-end devices containing both M9K RAM (9Kbit) and M-144K (144Kbit) structures simultaneously.
In addition to RAM, FPGAs from Altera, Xilinx, and Lattice can also flexibly configure LUTs as RAM, ROM, FIFO, and other storage structures, a technique known as distributed RAM.
4. Abundant Routing Resources:
Routing resources connect all units within the FPGA, and the length and technology of the connections determine the driving capability and transmission speed of signals on the connections. There are three types of routing resources available:
(1) Global dedicated routing resources: used to complete the routing of global clocks and global resets/set signals within the device.
(2) Long line resources: used for routing some high-speed signals and secondary global clock signals between device banks.
(3) Short line resources: used for logical interconnections and routing between basic logic units.
(4) Various routing resources and dedicated clock, reset, and other control signal lines also exist within the basic logic units.
5. Underlying Embedded Functional Units:
General-purpose embedded functional modules, such as PLL (Phase Locked Loop), DLL (Delay Locked Loop), DSP, and CPU.
Altera chips integrate PLL, Xilinx chips mainly integrate DLL, and Lattice’s new FPGAs integrate both PLL and DLL to meet different needs.
Altera’s PLL module is divided into enhanced PLL and fast PLL.
Xilinx’s DLL module is named CLKDLL, and in high-end FPGAs, the enhanced module of CLKDLL is called DCM (Digital Clock Manager).
6. Embedded Dedicated Hard Cores:
Embedded dedicated hard cores have relatively low generality; not all FPGA devices contain hard cores.
There are also two camps within FPGAs: on one hand, there are FPGAs with high generality, a wide target market range, and moderate prices; on the other hand, there are FPGAs with strong targeting, clear target markets, and higher prices.
