As the infrastructure based on the Arm architecture continues to expand across various markets, the demands on system components are also increasing. This means a significant rise in the number of interrupts (signals sent to the processor by hardware or software, requesting a pause of the current task to handle another task). Arm’s Generic Interrupt Controller architecture (GIC) has always been dedicated to efficiently managing communication between devices and processors, ensuring that the correct processor handles the correct task at the right time, and prioritizing important tasks. Today, we welcome a major evolution of this architecture—GICv5.
GICv5 is a redesigned architecture aimed at meeting the stringent demands of modern computing. It not only supports simpler hypervisors with a smaller Trusted Computing Base (TCB) but also improves power management features and enhances support for system partitioning.
1. Addressing the Scaling Challenges of Large-Scale Systems
The number of cores in modern systems is evolving towards hundreds, which is a significant leap compared to the configurations targeted by GICv3 and GICv4 designs. Previous GIC architectures faced integration bottlenecks when deployed in large-scale systems, such as arbitrary limits on the number of wired interrupts and the need for globally memory-mapped I/O (MMIO) registers, which added complexity to hardware design and software programming.
GICv5 directly addresses these challenges, bringing:
- Unlimited Wired Interrupts: Completely eliminates the quantity limitations of previous architectures.
- No Global Synchronization for MMIO Registers: Simplifies hardware design and reduces software programming complexity.
- Redesigned Programming Model: Supports smooth scaling from single-core to hundreds of cores.
- Dynamic Scalability of Interrupts: The system can flexibly adjust based on actual demand.
2. Significant Leap in Virtualization Performance
In GICv3, most interrupt-related operations (such as handling, configuring, and inter-processor signaling) required entering Exception Level 2 (EL2), which is the hypervisor level. This not only increased latency but also polluted caches and predictors. GICv4 made significant progress by supporting direct injection of Message Signaled Interrupts (MSI) and Inter-Processor Interrupts (IPI), especially in GICv4.1, which brought substantial performance improvements for interrupt-intensive workloads and IPI-intensive application scenarios.
GICv5 completely eliminates virtualization overhead, meaning:
- All Interrupt Types Support Direct Injection, without hypervisor intervention.
- Sending or Receiving IPIs No Longer Requires Entering the Hypervisor.
- Reading and Updating Interrupt Configurations Can Be Done Entirely Outside of EL2.
These advantages make virtualization-based system partitioning possible. This is a promising technology that can integrate real-time sensitive workloads with more complex workloads on the same chip through virtualization. For example, GICv5 allows real-time operating systems (RTOS) to run in parallel with feature-rich operating systems (like Linux), enabling both vehicle control functions and in-car entertainment functions to coexist on the same SoC.
3. Deep Integration with Arm’s Confidential Computing Architecture
In GICv3 and GICv4, interrupt virtualization required hypervisor intervention. Since the GIC emulation for “realms” was done in the hypervisor of the “normal world,” the trap cost was higher than that of conventional virtual machines (VMs). This increased overhead and forced critical interrupt functions to rely on untrusted hypervisors.
GICv5 can perform common interrupt operations without hypervisor intervention, allowing the GICv5 emulation and support code to be implemented in the Realm Management Monitor (RMM), thereby minimizing the impact on the TCB. This enables:
- Interrupts to Be Delivered Directly to the “Realm” Without EL2 Involvement.
- The “Realm” Experiences the Same Interrupt Handling Process as Non-Realm Virtual Machines.
- The “Realm” Fully Owns the GIC Interface, including the memory that saves its interrupt state.
- Combining RME Device Allocation (RME-DA) Technology, interrupts can achieve end-to-end confidentiality and integrity protection.
4. Profound Impact on Hardware and Software
GICv5 brings significant changes to both hardware and software.
- Hardware Level: The traditional “Distributor” and “Redistributor” are replaced by a new “Interrupt Routing Service” (IRS). It also adopts a simplified ITS model and a new “Interrupt Line Bridge” (ILB) to convert wired signals.
- CPU Interface: Equipped with new system instructions to improve interrupt handling and avoid entering EL2. It also utilizes Arm’s memory model tools to support relaxed memory ordering.
- Compatibility and Ecosystem: The new GIC Stream protocol ensures interoperability between the CPU interface and IRS. Although the programming model is not backward compatible, GICv5 includes a virtual CPU interface to support existing operating systems in virtual machines. Arm will provide updated firmware, Linux/KVM support, and virtual platforms to accelerate the development process.
The launch of GICv5 marks a new era in interrupt management, laying a solid foundation for building a more powerful, secure, and flexible Arm computing ecosystem.
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