Instruction sets can be divided into Complex Instruction Set Computing (CISC) and Reduced Instruction Set Computing (RISC), represented by the architectures x86, ARM, and MIPS.
ARM RISC is a chip architecture designed to improve processor speed, with key technology in pipelining, which allows multiple instructions to be completed in one clock cycle. Compared to Complex Instruction Set Computing (CISC), the ARM instruction set, based on RISC architecture, has a unified instruction format, fewer types, and fewer addressing modes. The simplicity of the instructions allows for the hardware lines to be optimized, thereby increasing execution speed. Due to the simplified instruction set, many tasks must combine simple instructions, while complex combinations require the compiler to execute. In contrast, the x86 instruction set of the CISC architecture has a wider range of instructions provided by the hardware, allowing many tasks to be replaced by one or a few instructions, significantly reducing compilation work.
The main characteristics of the ARM instruction set architecture are: first, small size, low power consumption, low cost, and high performance; second, extensive use of registers with most data operations completed in registers, resulting in faster instruction execution; third, flexible and simple addressing modes, leading to high execution efficiency; fourth, fixed instruction length, which can improve processing efficiency through multiple pipelines.
MIPS is an architecture in high-efficiency Reduced Instruction Set Computing, which has several advantages compared to the commercially successful ARM architecture: first, MIPS supported 64-bit instructions and operations earlier than ARM. To date, MIPS has released the P5600, I6400, and M5100 series of 64-bit processor architectures for high, medium, and low-end markets, with single-core performance reaching 3.5 and 3.0 DMIPS/MHz for P5600 and I6400, respectively, processing 3.5 million and 3 million instructions per second, exceeding the ARM Cortex-A53’s 2.3 million instructions per second; second, MIPS has a dedicated divider that can execute division instructions; third, MIPS has twice as many core registers as ARM, leading to lower power consumption at the same performance level, and higher performance at the same power consumption; fourth, MIPS has slightly more instructions than ARM, allowing for more flexible execution of certain calculations; fifth, MIPS is more open in architecture licensing, allowing licensees to modify designs, such as designing more cores.
However, the MIPS architecture also has some shortcomings: first, MIPS has issues with memory address starting points, leading to limitations in memory and cache support, meaning a single MIPS core cannot handle high-capacity memory configurations; second, MIPS’s technological evolution is towards parallel threads, similar to Intel’s hyper-threading, while ARM’s future direction is physical multi-core, which currently dominates the development trend of mobile devices; third, although MIPS has a simpler structure, it still operates on single/double dispatch, whereas ARM has evolved to out-of-order double/triple dispatch, making instruction pipeline cycles far less efficient than ARM; fourth, MIPS’s academic development style has caused its commercial progress to lag behind ARM, as ARM collaborates with chip design companies like Qualcomm, Apple, and NVIDIA to aggressively attack mobile terminals, while MIPS remains focused on niche market products like high-definition boxes and printers; fifth, MIPS’s own software platform is relatively outdated, with far fewer application software options compared to the ARM architecture.
x86 CISC is a chip design system aimed at facilitating programming and improving memory access efficiency, characterized by two main features: first, it uses microcode, allowing the instruction set to be executed directly from microcode memory. Newly designed processors only need to add a few transistors to execute the same instruction set and can quickly write new instruction set programs; second, it has a vast instruction set, including various instruction types such as dual operand formats, register-to-register, register-to-memory, and memory-to-register, enabling complex operations. The microprocessor provides various registers and machine instruction functions to programmers and achieves powerful functionality through microprograms stored in read-only memory (ROM). After analyzing each instruction, the microprocessor executes a series of basic instruction operations to fulfill the required functions.
The advantages of the x86 instruction system are reflected in its ability to effectively shorten the microcode design time for new instructions and allow for upward compatibility of CISC architecture machines, enabling new systems to use a set of instructions that includes those from earlier systems. Additionally, the format of microprogram instructions matches higher-level languages, meaning compilers do not necessarily need to be rewritten. Compared to the ARM RISC instruction set, its disadvantages mainly include four aspects.
First, the scale of general-purpose registers is small; the x86 instruction set only has eight general-purpose registers, and the CPU spends most of its time accessing data in memory, affecting the overall system execution speed. In contrast, RISC systems often have many general-purpose registers and use techniques such as overlapping register windows and register files to fully utilize register resources.
Second, the decoder affects performance; its role is to convert variable-length x86 instructions into fixed-length instructions similar to RISC and pass them to the RISC core. Decoding can be divided into hardware decoding and micro-decoding; for simple x86 instructions, hardware decoding suffices, which is fast, while complex x86 instructions require micro-decoding, splitting them into several simple instructions, which is slower and more complicated.
Third, the addressing range of the x86 instruction set is limited, constraining user needs.
Fourth, x86 CISC has variable instruction lengths, which provide powerful computing capabilities but make the structure complex, making it challenging to integrate all CISC hardware onto a single chip. In contrast, ARM RISC has fixed instruction lengths, containing only a few frequently used instructions, generally lower performance but simpler structure and stable execution efficiency.
[This article is sourced from: “Storage” and Sina Weibo Vincent Weimin. For details, please click the lower left corner “Read Original”]