Selected community article series “AI Ignites Chip Revolution, Capitalizing on New Opportunities in Advanced Packaging” Original Author:Shu Shu, Original Link:
https://www.24krmb.com/thread-4322-1-1.htmlHello everyone, today I want to discuss a particularly hot topic—the new opportunities in chip packaging brought about by AI. It can be said that the demand for intelligent computing is surging, and the packaging segment is also rising rapidly, ushering in its own moment of glory.
Why do I say this? I believe everyone has felt it; starting in 2024, major internet companies are accelerating their layout of large models, especially with technological breakthroughs like DeepSeek, which have significantly lowered the barriers for application. Now, various AI agents are becoming increasingly mature. This directly drives the rapid growth of intelligent computing power in China.
How fast is it? According to the IDC report titled “2025 China Artificial Intelligence Computing Power Development Assessment Report,” by 2024, China’s intelligent computing power scale will reach 725.3 EFLOPS. You might not have a concept of this number, but look at the growth rate, which has increased by 74.1% year-on-year! This increase is more than three times that of general computing power during the same period. Moreover, in the next two years, this rapid growth momentum will not diminish at all; the report predicts, by 2025, the scale will reach 1037.3 EFLOPS, an increase of 43% from 2024; by 2026, this number will be 1460.3 EFLOPS, nearly double that of 2024! You see, this growth curve is very steep.
Not only is computing power increasing, but the application of large models in enterprises is also truly starting to scale up. According to FROST & SULLIVAN’s insight report, in the first half of 2025, the daily call volume of enterprise-level large models in our country has reached 100 trillion tokens. Do you know how much it was half a year ago, in the second half of 2024? It was 220 million tokens. Calculating this, it has increased by about 363%, showing a very significant scaling trend. What does this indicate? It indicates that large models have quickly passed the early pilot and validation stages and have truly entered a new period of large-scale implementation. The direct result is that the consumption of basic resources such as computing power and storage will increase significantly.
This wave of AI has also become the strongest driving force in the semiconductor market. Previously, TSMC announced very bright performance for the second quarter of 2025, with revenue and net profit both showing high growth year-on-year and quarter-on-quarter. TSMC’s executives also stated that this is mainly due to the sustained strong demand related to AI and high-performance computing. Looking at our domestic situation, the capacity utilization rates of the two major foundries are also continuously climbing in 2025; Huahong Semiconductor’s comprehensive capacity utilization rate reached 108.30% in the second quarter, and SMIC’s 8-inch wafer utilization rate also reached 92.50%. Behind this is the demand driven by high-performance computing.
With such strong demand for computing power, the market scale and share of AI chips are also continuously growing. Some analyses predict that the capacity share of AI chips in advanced processes will increase from only 2% in 2022 to 4% in 2024, and is expected to reach 7% by 2027. Its contribution to the overall foundry industry’s output value is rapidly increasing. There are also predictions that the market scale of AI chips in China will surge from over 140 billion yuan in 2024 to 1.34 trillion yuan in 2029, with an average annual compound growth rate exceeding 53%. This market space is enormous.
So the question arises, AI chips have extremely high performance requirements, needing high integration, small area, and low power consumption; how can this be achieved? This is where advanced packaging technology comes into play. To meet the computing power demands of large models and break through traditional bottlenecks like the “memory wall” and “area wall,” advanced packaging through high-density integration has become a key path to enhance chip performance. For example, you may have heard of HBM (High Bandwidth Memory) and GPUs, which are integrated together using 2.5D packaging technology, successfully breaking the “memory wall”; while HBM itself utilizes 3D stacking and TSV (Through-Silicon Via) technology to significantly shorten data transmission distances and reduce power consumption.
The current situation is that the explosive demand for AI chips has directly led to a shortage of advanced packaging. Reports indicate that at TSMC’s shareholder meeting, the company clearly stated that AI order demand has suddenly increased, and the demand for advanced packaging far exceeds existing capacity, forcing the company to urgently increase production capacity. High-performance computing customers like NVIDIA have very strong orders, all requesting TSMC to expand the capacity of advanced packaging like CoWoS, leading to a gap of 10% to 20%. TSMC is also actively expanding production; its CoWoS packaging capacity is expected to expand to over 90,000 wafers per month by the end of 2026, with a compound annual growth rate of 50%. This expansion speed itself also indicates the booming demand.
Let’s return to the packaging technology itself. Driven by strong demands from AI large models, data centers, and intelligent driving, the global advanced packaging industry has ushered in unprecedented development opportunities. The current technological paths are very diverse, ranging from basic bump and redistribution layer processes to flip-chip, wafer-level packaging, and even more advanced 2.5D/3D stacking, creating a comprehensive technological architecture. Data shows that the global advanced packaging market size will leap from $46.1 billion in 2024 to $79.1 billion in 2030. Among them, the growth of 2.5D/3D packaging technology will be particularly rapid, serving as the core engine driving the entire industry upgrade.
In China, the packaging and testing market is also shifting from past “scale expansion” to “technology-ecological comprehensive competition.” In 2024, the National Big Fund Phase II will also focus on enhancing the packaging and testing segment, especially supporting advanced packaging projects below 28 nanometers. Driven by both policy and demand, the window period for domestic substitution has fully opened.
Specifically at the technical level, advanced packaging is also rapidly iterating. Overall, two major trends are very obvious: one is miniaturization, shifting from planar packaging to 2.5D/3D stacked packaging, making chips thinner to meet the needs of portable devices; the other is high integration, through three-dimensional stacking and heterogeneous integration, integrating multiple chips with different functions into one package, greatly improving integration and data transmission speed.
To achieve these, there are many specific technical paths. For example, at the single-chip level, there is flip-chip bonding technology, which eliminates traditional leads, allowing the chip to connect directly to the substrate, thus shortening the interconnection distance to the micron level, reducing resistance by 90%, and supporting higher frequencies. Wafer-level packaging is also in pursuit of miniaturization and efficiency. In multi-chip integration, concepts like 2.5D, 3D, and Chiplet are very popular. Here, we must mention a basic process called Bumping, which involves creating tiny solder ball bumps on the wafer; it is a fundamental interconnection component for connecting chips and substrates, and the cost share of this process is quite high.
Among the many technical solutions, TSMC’s CoWoS is a well-known 2.5D/3D packaging technology that saves space and reduces power consumption by stacking chips and packaging them onto a substrate. Additionally, there is InFO (Integrated Fan-Out) packaging, which uses a special material to replace the silicon interposer, reducing costs and packaging height, achieving great success in mobile applications and high-performance computing markets. TSMC’s SoIC technology can achieve higher density 3D integration, significantly reducing packaging space and thickness; it is said that under advanced processes, it can double the performance within nearly the same volume.
The next generation of technical solutions is also advancing rapidly. For example, there have been recent reports that NVIDIA has upgraded CoWoS by eliminating the packaging substrate and solder balls, introducing a technology called CoWoP. This simplifies the structure, shortening the signal transmission path by about 40%, along with other performance advantages. It is expected that by 2026, we may see a parallel packaging strategy of CoWoS and CoWoP.
Finally, let’s take a brief look at a few representative companies in the market. For example,
Changdian Technology, a global leading packaging and testing service provider, has a very comprehensive technology system covering wafer-level packaging, 2.5D/3D packaging, etc., and has made breakthroughs in cutting-edge technologies such as glass substrates and optoelectronic co-packaging.
Tongfu Microelectronics, also a domestic leader, has a wide range of businesses and multiple production bases globally, with a rich variety of packaging types, achieving significant progress in large-size chip packaging and optoelectronic co-packaging fields.
There is also Jingfang Technology, a leader in wafer-level packaging technology, particularly focused on the sensor field, such as CIS chip packaging for automobiles, with clear advantages, while also expanding its business in optical devices.
The wave of AI is profoundly changing the landscape of the chip industry, especially bringing tremendous development opportunities and innovative vitality to the advanced packaging segment. In the future, as our demand for computing power is endless, packaging technology will continue to evolve, bringing more possibilities.
I hope the above sharing can help everyone gain a more intuitive understanding of this field.
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