1. What is ARM Cortex-M Processor

1.1 Cortex-M3 and Cortex-M4 Processors

Cortex-M3 (released in 2005) and Cortex-M4 (released in 2010) processors are designed by ARM.

Cortex-M3 and Cortex-M4 processors use a 32-bit architecture, with internal registers, data, and bus interfaces all being 32-bit. The instruction set architecture (ISA) used by Cortex-M processors is Thumb ISA (a RISC – Reduced Instruction Set), based on Thumb-2 technology, supporting both 16-bit and 32-bit instructions.

They have the following main features:

• Three-stage pipeline: fetch, decode, execute.
• Harvard bus architecture, meaning it has a unified memory space: instruction and address bus use the same address space.
• 32-bit addressing, supporting 4GB memory space
• Has an interrupt controller named NVIC (Nested Vectored Interrupt Controller), supporting up to 240 interrupt requests and 8-256 interrupt priorities.
• Supports various OS features, such as the SysTick timer, shadow stack pointers (dual stack pointers: MSP/PSP).
• Sleep mode and various low-power features.
• Supports optional MPU (Memory Protection Unit), providing memory access control.
• Supports bit-field access for two specific memory regions.

Cortex-M3 and M4 processors provide various instructions:

• General data processing, including hardware division instructions.
• Memory access instructions, supporting 8-bit, 16-bit, 32-bit, and 64-bit data, as well as other instructions that can transfer multiple 32-bit data.
• Bit-field processing instructions.
• Multiply-accumulate (MAC) and saturation instructions.
• Instructions for jumps, conditional jumps, and function calls.
• Instructions for system control, supporting OS, etc.

Additionally, the M4 processor also supports:

• Single Instruction Multiple Data (SIMD) instructions.
• Other fast MAC and multiplication instructions.
• Saturation operation instructions.
• Optional single-precision floating-point instructions.

1.2 Cortex-M Processor Family

Cortex-M3 and Cortex-M4 processors are based on the ARMv7-M architecture. The Cortex-M4 processor has SIMD, fast MAC, and saturation instructions, allowing it to execute some array signal processing programs.

Cortex-M0, Cortex-M0+, and Cortex-M1 are based on the ARMv6-M architecture. Cortex-M1 is specially designed for FPGA applications.

Cortex-M33 is based on the ARMv8-M architecture, adding security components such as TrustZone.

1.3 Difference Between Processor and Microcontroller

In a typical microcontroller design, the processor occupies only a small area of the chip. The other parts include memory, clock generation (like PLL), distribution logic, system bus, and peripherals (I/O interface units, communication interfaces, timers, ADC, DAC, etc.). Microcontroller vendors (like ST, TI, NXP) choose Cortex-M processors as their CPU, adding the aforementioned functional units, ultimately forming a microcontroller. As shown in the figure below:

1.4 Development of ARM Processors

Before the release of the Cortex-M3 processor, there were many types of ARM processors, such as ARM7, ARM9, ARM11. They support two sets of instruction sets: the 32-bit ARM instruction set and the 16-bit Thumb instruction set.

Currently, the Cortex processor series includes three categories:

• Cortex-A for high-performance development application platforms.
• Cortex-R for high-end embedded systems requiring real-time performance.
• Cortex-M for embedded microcontroller systems.

1. Cortex-A: Application processors for complex applications requiring high-end embedded systems (OS like iOS, Android, Linux, and Windows), needing powerful processing capabilities, supporting memory management units (MMU) and other virtual memory systems, optionally enhanced Java support, and secure program execution environments. Actual products include high-end smartphones, tablets, TVs, and servers.
2. Cortex-R: Real-time, high-performance processors targeting the higher-end real-time market, applications include disk controllers, baseband controllers for mobile communications, and automotive systems. Strong processing power and high reliability are critical, with low interrupt latency and determinism also being very important.
3. Cortex-M: Targeting microcontrollers and mixed-signal designs for small applications, focusing on low cost, low power consumption, energy efficiency, and low interrupt latency.

1.5 Thumb ISA Architecture Versions

2. Software Development Process

3. Technical Overview

3.1 General Information on Cortex-M3 and M4 Processors

3.1.1 Processor Type

Cortex-M3 and M4 are 32-bit RISC (Reduced Instruction Set) processors that feature:

• 32-bit registers
• 32-bit internal data paths
• 32-bit bus interfaces

Cortex-M3 and M4 have a three-stage pipeline, based on Harvard bus architecture (the other being Princeton architecture), allowing instruction fetch and data access to occur simultaneously. The memory system uses 32-bit addressing, with a maximum address space of 4GB. The memory space includes program code, data, peripherals, and internal debugging support components.

Cortex-M processors are based on a load-store architecture. For example, to increase the stored value in SRAM, the processor needs an instruction to read the data from SRAM, load it into a processor register, then use a second instruction to increase the value in the register, and finally use a third instruction to write it back to memory.

3.1.2 Instruction Set

The instruction set used by Cortex-M processors is Thumb-2, which runs a mix of 16-bit and 32-bit instructions to achieve higher code density and efficiency.

Classic ARM processors (like ARM7) have two operating states: 32-bit ARM state and 16-bit Thumb state. In ARM state, the instructions are 32-bit, allowing the core to execute all supported instructions with high performance; for Thumb state, the instructions are 16-bit, achieving good code density, but Thumb instructions do not have all the functionalities of ARM instructions, requiring more instructions to perform specific operations. As shown in the figure. For classic ARM processors, interrupt handling enters ARM state.

With the introduction of Thumb-2 technology, Thumb instructions were extended to support both 16-bit and 32-bit decoding methods, eliminating the need to switch between two different operating states to meet all processing needs.

3.1.3 Module Block Diagram

3.1.4 Memory System

Cortex-M3 and M4 processors do not contain memory themselves; they have a generic on-chip bus interface, allowing vendors to add their own memory systems to the system. The components include:

• Program memory, typically Flash
• Data memory, typically SRAM
• Peripherals

The primary bus interface protocol used by Cortex-M3 and M4 processors is AHB Lite (Advanced High-performance Bus), which is used for program memory and system bus interfaces. The Advanced Peripheral Bus (APB) interface is another bus protocol used by the processor.

3.1.5 Interrupt and Exception Support

There is a Nested Vectored Interrupt Controller (NVIC) in Cortex-M3 and M4 processors. It is programmable and its registers are memory-mapped. Its address is fixed, and the programming model is consistent across all Cortex-M processors.

In addition to peripherals and other external interrupt inputs, NVIC also supports multiple system exceptions, including NMI (Non-Maskable Interrupt). Vendors decide the actual number of programmable interrupt priorities supported.

4. Architecture

4.1 Programming Model

4.1.1 Operating Modes

Figure 4.1 Operating States and Modes

• Handler Mode: Executes ISR and other exception handling. In this mode, the processor always has privileged access level.
• Thread Mode: When executing normal application code, the processor can be in either privileged or unprivileged access level. The actual access level is controlled by a special register (CONTROL).

Software can switch the processor from privileged thread mode to unprivileged thread mode, but cannot switch itself from unprivileged to privileged mode without using the exception mechanism.

By distinguishing between privileged and unprivileged access levels, designers can provide protection mechanisms for accessing critical areas and a basic security model, which helps in developing robust embedded systems. For example, the system might include an OS kernel running at a privileged access level, and applications running at an unprivileged access level. The MPU can also be used to set memory access permissions to prevent application tasks from corrupting the memory and peripherals used by the OS kernel and other tasks. If an application task crashes, the remaining tasks and the OS kernel can continue running.

Almost all NVIC registers support privileged access.

4.1.2 Registers

The register group contains 16 registers, among which 13 are 32-bit general-purpose registers, and the other 3 have special purposes, as shown in the figure:

Figure 4.2 Registers in the Register Group

1. R0 – R12

   The first 8 (R0 – R7) are low registers. Many 16-bit instructions can only access low registers. High registers (R8 – R12) can be used for 32-bit instructions and some 16-bit instructions. R0 – R12 initial values are undefined.

2. R13 (SP)

   R13 is the stack pointer, allowing access to stack storage via PUSH and POP instructions. There are 2 stack pointers: the main stack pointer (MSP) is the default stack pointer used during reset or when the processor is in handler mode; the other is the process stack pointer (PSP), which can only be used in thread mode. The choice of stack pointer is determined by a special register (CONTROL). Both MSP and PSP are 32-bit, but the lowest two bits of the stack pointer are always 0. PUSH and POP are always 32-bit and aligned to 32-bit words.

3. R14 (LR)

   R14 is the link register, used to save the return address during function or subroutine calls. In exception handlers, LR is automatically updated to a special EXC_RETURN value, which triggers the exception return when the exception handling ends. Some jump/call operations require setting the 0th bit of LR (or any register in use) to 1 to indicate Thumb state.

4. R15 (PC)

   R15 is the program counter.

4.1.3 Special Registers

In addition to the registers in the register group, there are several special registers in the processor, as shown in the figure:

Figure 4.3 Special Function Registers

Special registers are not memory-mapped and can be accessed using special register access instructions like MSR and MRS.

MRS <reg>, <special_reg> ; Read special register into register
MSR <special_reg>, <reg> ; Write to special register

1. Program Status Register

The program status register includes the following three status registers:

• Application PSR (APSR)
• Execution PSR (EPSR)
• Interrupt PSR (IPSR)

Figure 4.4 APSR, IPSR, and EPSR

1. PRIMASK, FAULTMASK, and BASEPRI Registers

PRIMASK, FAULTMASK, and BASEPRI registers are used for exception or interrupt masking, with each exception having a priority, where lower values indicate higher priority. These special registers can mask exceptions based on priority and can only be accessed at privileged access levels. The programming model for these registers is as follows:

Figure 4.5 PRIMASK, FAULTMASK, and BASEPRI Registers

• When PRIMASK is set, it prevents all exceptions except NMI and HardFault. The most common use is to disable all interrupts in time-critical processes; after the process is completed, it needs to be cleared to re-enable interrupts.
• FAULTMASK is very similar to PRIMASK, but it can also mask HardFault exceptions. Error handling code can use FAULTMASK to prevent other errors from occurring during error handling. FAULTMASK is automatically cleared on exception return.
• BASEPRI masks interrupts based on priority. Its width depends on the number of programmable priorities implemented in the actual chip; most have 8 or 16 programmable priorities, corresponding to widths of 3 or 4 bits. BASEPRI does not work when it is 0; when non-zero, it masks exceptions with the same or lower priority.

CMSIS-Core provides several C functions to access them.

x = _get_BASEPRI(); // Read BASEPRI register
x = _get_PRIMASK(); // Read PRIMASK register
x = _get_FAULTMASK(); // Read FAULTMASK register
_set_BASEPRI(x); // Set new value for BASEPRI register
_set_PRIMASK(x); // Set new value for PRIMASK register
_set_FAULTMASK(x); // Set new value for FAULTMASK register
_disable_irq(); // Set PRIMASK, disable IRQ
_enable_irq(); // Clear PRIMASK, enable IRQ

These exception masking registers can also be accessed using assembly code:

MRS r0, BASEPRI; // Read BASEPRI register into R0
MRS r0, PRIMASK; // Read PRIMASK register into R0
MRS r0, FAULTMASK; // Read FAULTMASK register into R0
MSR BASEPRI, r0 ; // Write R0 into BASEPRI register
MSR PRIMASK, r0 ; // Write R0 into PRIMASK register
MSR FAULTMASK, r0 ; // Write R0 into FAULTMASK register

Additionally, the processor state can be modified using the CPS instruction:

CPSIE i ; Enable interrupts (clear PRIMASK)
CPSID i ; Disable interrupts (set PRIMASK)
CPSIE f ; Enable interrupts (clear FAULTMASK)
CPSID f ; Disable interrupts (set FAULTMASK)

1. CONTROL Register

The CONTROL register (as shown in the figure) defines:

• The choice of stack pointer (MSP/PSP)
• The access level of thread mode (privileged/unprivileged)

The CONTROL register can only be modified at privileged access level, while read operations can be performed at both privileged and unprivileged levels.

Figure 4.6 CONTROL register in Cortex-M3, Cortex-M4, and Cortex-M4 with FPU

Table 4.1 Bit Fields in CONTROL Register

After reset, the CONTROL register defaults to 0, meaning that the processor is in privileged access level thread mode and uses MSP. By writing to the CONTROL register, programs in privileged thread mode can switch the stack pointer or enter unprivileged access level. However, once the nPRIV bit is set, programs running in thread mode cannot access the CONTROL register. Thus, programs running at unprivileged level cannot switch back to privileged level, providing a basic security model; if necessary, to switch the processor back to privileged level in thread mode, the exception mechanism is required. The nPRIV bit is cleared during exception handling, and when returning to thread mode, the processor will enter privileged level.

Figure 4.7 Stack Pointer Selection

Figure 4.8 Switching Between Privileged Thread Mode and Unprivileged Thread Mode

4.1.4 Floating-Point Registers

Cortex-M4 has an optional floating-point unit, providing some registers for floating-point data processing and floating-point status and control registers (FPSCR).

1. S0 – S31 and D0 – D15
2. Floating-Point Status and Control Register (FPSCR)

4.2 Memory System

4.2.1 Memory Mapping

The 4GB address space of Cortex-M processors is divided into several memory regions, as shown in the figure. The regions are classified based on their usage, mainly for:

• Program code access (e.g., CODE region)
• Data access (e.g., SRAM region)
• Peripherals (e.g., peripheral region)
• Internal control and debugging components of the processor (e.g., private peripheral bus)

This architectural arrangement provides great flexibility; memory regions can be used for other purposes. For example, programs can execute in either CODE or SRAM regions, and microcontrollers can also add SRAM in the CODE region.

Figure 4.9 Memory Mapping

4.2.2 Stack Storage

In a stack memory mechanism, a portion of memory can be used as a last-in-first-out data storage buffer. ARM processors use the system main memory for stack space operations, using PUSH and POP. After each PUSH and POP operation, the stack pointer is automatically adjusted.

The stack can be used for:

• Temporarily storing initial values of data when a function being executed needs to use registers for data processing. These values can be restored at the end of the function.
• Passing information to functions or subroutines, i.e., passing parameters during function calls.
• Storing local variables.
• Saving processor state and register values during interrupts and other exceptions.

Cortex-M processors use a “full descending” stack model. After the processor starts, SP is set to the last position of the stack storage space. For each PUSH operation, the processor first decreases the value of SP, then stores data at the memory location pointed to by SP. For POP operations, data at the memory location pointed to by SP is read out, and then the value of SP is automatically decreased.

The most common use of PUSH and POP instructions is to save the contents of the register group when executing a function call, and restore their values via POP when the function call ends.

In embedded systems that include an OS, the stack space used by application tasks and the kernel is usually separated, so PSP will be used. During exception entry and exit, SP switching occurs, as shown in the figure below.

Figure 4.11 SPSEL=1, thread level uses process stack while exception handling uses main stack

Although only one SP is visible at a time, if currently at privileged level, hidden SP can be accessed using PSR and MRS instructions.

4.3 Exceptions and Interrupts

4.3.1 What are Exceptions

Cortex-M processors have multiple sources of exceptions, as shown in the figure:

Figure 4.12 Various Sources of Exceptions

1. NVIC Handles Exceptions. NVIC can handle multiple interrupt requests (IRQ) and one non-maskable interrupt (NMI) request. IRQs are generally generated by on-chip peripherals or external interrupt inputs through I/O ports, while NMI can be used for watchdog or power-down detection. The processor has an internal timer called SysTick, which can generate periodic interrupt requests for OS timing.
2. The processor itself is also a source of exceptions, including error events indicating system error states and exceptions generated by software, supporting OS operations. The types of exceptions are as follows:

Table 4.2 Types of Exceptions

Each exception source has a unique exception number, with numbers 1-15 representing system exceptions, and 16 and above used for interrupts. Cortex-M4 and M4 are designed to support up to 240 interrupt inputs, but the actual number of implemented interrupts is usually much lower, generally between 16-100.

4.3.2 NVIC

NVIC manages exceptions and interrupts configuration, priority, and interrupt masking. NVIC has the following features:

• Flexible exception and interrupt management
• Support for nested exceptions/interrupts
• Vectorized exception/interrupt entry
• Interrupt masking

4.3.3 Vector Table

When an exception event occurs and is accepted by the processor core, the corresponding exception handler will execute. The vector table is relocatable and is controlled by a register in NVIC called the Vector Table Offset Register (VTOR). By default, it is set to 0 after a reset, meaning the vector table is located at address 0x0.

Figure 4.13 Types of Exceptions (The least significant bit of the exception vector should be set to 1 to indicate Thumb state)

4.3.4 Error Handling

Several exceptions in Cortex-M3 and M4 processors are error handling exceptions. When the processor detects an error, it triggers an error exception, including executing an undefined instruction and bus errors, as well as errors returned from memory access.

Figure 4.14 Usage of Error Exceptions

Bus errors, usage errors, and memory management errors are disabled by default, and all error events will trigger HardFault exceptions (which are always enabled). However, these configurations are programmable.

4.4 Reset and Reset Process

For a typical Cortex-M processor, there are three types of reset:

• Power-on reset. Resets all parts of the microcontroller, including the processor, debugging support components, and peripherals.
• System reset. Only resets the processor and peripherals, excluding debugging support components.
• Processor reset. Resets only the processor.

After reset and before the processor begins executing programs, Cortex-M processors read the first two words from memory, as shown in the figure. The vector table is located at the beginning of memory, and its first two words represent the initial value of MSP and the reset vector, indicating the starting address of the reset. Reading these two words assigns them to MSP and PC.

Setting MSP is essential because there is a possibility of generating NMI or HardFault during reset, and MSP is required for stack storage when pushing the processor state during exception handling.

Figure 4.15 Reset Process

Figure 4.16 Initial Values of Stack Pointer and Program Counter

5 Memory System

5.1 Memory Mapping

Figure 5.1 Predefined Memory Mapping of Cortex-M3 and Cortex-M4 Processors (Shaded parts are used for debugging)

5.2 Connecting Processor to Memory and Peripherals

Figure 5.2 Multiple Bus Interfaces for Different Memory Regions

Figure 5.3 Simple System Based on Cortex-M3 or Cortex-M4

Figure 5.4 Flash Access Accelerator Diagram for STM32F4

Figure 5.5 Multi-layer AHB Example (NXP LPC1700)

5.3 Bit Field Operations

Figure 5.6 Bit Access to Bit Field Regions via Bit Field Aliasing (SRAM Region)

5.4 Memory Barriers

Memory barrier instructions: ISB, DSB, DMB

5.5 Memory System in Microcontrollers

Many microcontroller devices also integrate other memory system features in their designs. For example:

• BootLoader
• Memory Remapping
• Memory Aliasing

Figure 5.7 Simple Memory System with Configurable Memory Mapping

Figure 5.8 Memory Remapping Example in a System with Bootloader

6 Exceptions and Interrupts

6.1 Introduction to Exceptions and Interrupts

In a typical Cortex-M4 microcontroller, NVIC receives interrupt requests generated by multiple sources, as shown in the figure

Figure 6.1 Various Exception Sources in a Typical Microcontroller

The NVIC of Cortex-M3 and Cortex-M4 supports up to 240 IRQs, 1 NMI, 1 SysTick, and multiple system exceptions. Most interrupts are generated by peripherals such as timers, I/O ports, and communication interfaces (UART, I2C). Interrupts can also be generated by software.

To continue executing the interrupted program, the exception process needs to use some means to protect the state of the interrupted program so that it can be restored after exception handling is completed. Generally, this process can be implemented by hardware mechanisms or can be a combination of hardware and software operations. For Cortex-M4 processors, when an exception is accepted, some registers are saved to the stack, and they are automatically restored upon return.

6.2 Types of Exceptions

Numbers 1-15 represent system exceptions, while 16 and above represent interrupt inputs. Most exceptions, including interrupts, have programmable priorities, while some system exceptions have fixed priorities.

The interrupt source numbers (1-240) may differ among different Cortex-M4 microcontrollers, and their priorities may also vary.

Exception types 1-15 are system exceptions, as shown in Table 7.1. Types 16 and above are external interrupt inputs, as shown in Table 7.2.

Table 6.1 List of System Exceptions

Table 6.2 Interrupt List

CMSIS-Core defines the names of system exception handling.

Table 6.3 CMSIS-Core Exception Definitions

The priority configuration registers can be divided into two parts. The upper part (left bits) is for preemptive priority, while the lower part (right bits) is for sub-priority, as shown below:

Table 6.4 Common Basic Interrupt Control CMSIS-Core Functions

6.4 Priority Definition

Figure 6.2 3-bit Priority Register (8 Programmable Priorities)

Figure 6.3 4-bit Priority Register (16 Programmable Priorities)

The 8-bit register is divided into two parts: preemptive priority and sub-priority. Using a configuration register in the System Control Block (SCB) called the priority grouping, each priority configuration register with programmable priorities can be divided into two parts. The upper part (left bits) is for preemptive priority, while the lower part (right bits) is for sub-priority, as shown below:

Table 6.5 Definitions of Preemptive and Sub-Priority Fields in Priority Registers under Different Priority Groupings

Figure 6.4 Definitions of Priority Fields in 3-bit Priority Register when Priority Grouping is 5

Figure 6.5 Definitions of Priority Fields in 3-bit Priority Register when Priority Grouping is 1

Figure 6.6 Definitions of Priority Fields in 8-bit Priority Register when Priority Grouping is 0

6.5 Vector Table and Vector Table Relocation

When the Cortex-M processor accepts an exception request, it determines the starting address of the exception handler. This information is located in the vector table in memory, starting from address 0 by default, with vector addresses being the exception number multiplied by 4, as shown in the figure:

Figure 6.7 Vector Table

7 In-Depth Understanding of Exception Handling

7.1 Exception Handling Implemented in C

For Cortex-M processors, exception handling or ISRs can be implemented as ordinary C functions. To understand how this mechanism works, let’s take a look at how C functions work on the ARM architecture.

The C compiler for the ARM architecture follows a specification called AAPCS (ARM Architecture Procedure Call Standard). According to this standard, C functions can modify R0-R3, R12, R14, and PSR. If a C function needs to use R4-R11, it should save those registers to the stack and restore them before the function ends, as shown in the figure.

R0-R3, R12, R14, and PSR are called “caller-saved registers”. R4-R11 are called “callee-saved registers”; the called subroutine or function needs to ensure that these registers do not change at the end of the function. The values of these registers may change during function execution, but they must be restored before exiting the function. Generally, the function uses R0-R3 as input parameters, with R0 used as the return result. If the return value is 64 bits, R1 will also be used to return the result.

Figure 7.1 Register Usage in Function Calls as Defined by AAPCS

To enable C functions to be used as exception handlers, the exception mechanism needs to automatically save R0-R3, R12, R14, and PSR at the entry of the exception, and restore them upon exit, which must be controlled by the hardware of the stimulus.

Figure 7.2 Exception Stack Frame for Cortex-M3 or Cortex-M4 (without Floating Point) when No Double Word Stack Alignment is Required

7.1.1 EXC_RETURN

When entering exception handling or ISR, the value of LR will be updated to the value of EXC_RETURN. This value is used to trigger the exception return mechanism when loaded into PC via BX, POP, or memory load instructions (LDR or LDM).

Table 7.1 Bit Fields of EXC_RETURN

Table 7.2 Legal Values of EXC_RETURN

7.2 Exception Process

7.2.1 Exception Entry and Stack Push

Figure 7.3 Stack Push and Vector Fetch

Figure 7.4 Stack Push Process on AHB Lite Bus of Cortex-M3 Processor

Figure 7.5 Exception Stack Frame in Thread Mode Using Main Stack

Figure 7.6 Exception Stack Frame in Thread Mode Using Process Stack, and Nested Interrupt Stack Push Using Main Stack

7.2.2 Exception Return and Stack Pop

Figure 7.7 LR Set to EXC_RETURN During Exception (Thread Mode Using Main Stack)

Figure 7.8 LR Set to EXC_RETURN During Exception (Thread Mode Using Process Stack)

Figure 7.9 Stack Pop Operation

7.3 Interrupt Wait and Exception Handling Optimization

7.3.1 What is Interrupt Wait

7.3.2 Tail Chaining

If an exception occurs while the processor is handling another exception with the same or higher priority, the new exception will enter a pending state. After the processor completes the current exception handling, it can continue to process the pending exception/interrupt request. The processor does not restore registers from the stack (pop) and then store them in the stack (push); instead, it skips the pop and push process and enters the pending exception handling as quickly as possible, as shown in the figure. For a stateless memory system, the interrupt wait time for tail chaining is only 6 clock cycles.

Figure 7.10 Tail Chaining

7.3.3 Late Arrival

When an exception occurs, the processor accepts the exception request and begins the stack push operation. If a higher priority exception occurs during the push operation, the higher priority late arrival exception will be serviced first.

Figure 7.11 Late Arrival Exception Behavior

7.3.4 Stack Pop Preemption

If an exception request occurs during the stack pop operation of another recently completed exception handling, the processor will discard the pop operation and begin fetching the vector and the commands for servicing the next exception. This optimization is called stack pop preemption.

Figure 7.12 Stack Pop Preemption Behavior

7.3.5 Lazy Stack Push

Lazy stack push is a feature related to pushing floating-point unit registers onto the stack.

8 OS Support Features

8.1 Shadow Stack Pointer

Figure 8.1 Each Task’s Stack is Independent of Others

8.2 SVC Exception

Figure 8.2 Context Switching Simplified

Figure 8.3 SVC as an Entry Point for OS System Services

Figure 8.4 Using Assembly Language to Extract SVC Service Number

8.3 PendSV Exception

Figure 8.5 PendSV Context Switching Example

• The first part has a high time requirement and needs to execute quickly, so it has a higher priority. It is part of the normal ISR, and the PendSV is pending at the end of the ISR.
• The second part includes the remaining processing work required by the interrupt service, which is handled at a lower exception priority.

Figure 8.6 Using PendSV to Split Interrupt Service into Two Parts

8.4 Actual Context Switching

Figure 8.7 Context Switching

Figure 8.8 Task Switching Example in ucos-iii