15 Tips to Make FPGA Design So Easy

Basic Principles of Hardware Design

(1) Speed and Area Balance and Trade-off Principle: If a design has a large timing margin and can run at a frequency much higher than the design requirements, it can reduce the overall chip area consumption through module reuse, which is saving area in exchange for speed advantage; conversely, if a design has high timing requirements that cannot be met by conventional methods, it can process the design using data flow serialization and deserialization, parallel replication of multiple operation modules, adopting the ideas of “ping-pong operation” and “serialization/deserialization”. Then, data can be “deserialized” at the chip output module, thus achieving speed improvement in exchange for area replication.(2) Hardware Principles: Understand the essence of HDL;(3) System Principles: Grasp the whole;(4) Synchronous Design Principles: Basic principles for designing stable timing.

Verilog, as an HDL language, models system behavior in a hierarchical manner. Important levels include system level, algorithm level, register transfer level (RTL), logic level, gate level, and circuit switch level.

In actual work, for loop statements are rarely used in RTL coding except when describing simulation test stimuli (Testbench), as for loops will be expanded by synthesizers into execution statements for all variable cases, with each variable independently occupying register resources, which does not effectively reuse hardware logic resources and results in huge waste. Typically, case statements are used instead.

There is a significant difference between if…else… and case when nested descriptions are used. If…else… has priority; generally, the first if has the highest priority, and the last else has the lowest. In contrast, case statements are parallel statements with no priority; establishing a priority structure consumes a lot of logic resources, so if case can be used, if…else… statements should not be used.Supplement:1. You can also use if…; if…; if…; to describe parallel statements without priority.

FPGA generally has abundant trigger resources, while CPLD has richer combinational logic resources.

Composition of FPGA and CPLD:

FPGA is mainly composed of programmable I/O units, basic programmable logic units, embedded block RAM, abundant wiring resources, underlying embedded functional units, and embedded dedicated hard cores. CPLD has a relatively simple structure, mainly consisting of programmable I/O units, basic logic units, wiring pools, and other auxiliary functional modules.

Block RAM:

There are three types of block RAM structures: M512 RAM (512bit), M4K RAM (4Kbit), and M-RAM(64Kbit). M512 RAM: suitable for small buffers, FIFO, DPRAM, SPRAM, ROM, etc.; M4K RAM: suitable for general needs; M-RAM: suitable for buffering large data blocks. Xilinx and Lattice FPGA’s LUT can be flexibly configured into small RAM, ROM, FIFO, etc., a technology known as distributed RAM.Supplement: However, in general designs, it is not recommended to configure a large amount of memory using FPGA/CPLD on-chip resources due to cost considerations. Therefore, external memory should be used as much as possible.

Make good use of the chip’s internal PLL or DLL resources to complete operations such as clock division, frequency multiplication, and phase shifting, which not only simplifies the design but also effectively improves system accuracy and operational stability.

Differences Between Asynchronous Circuits and Synchronous Timing CircuitsAsynchronous Circuits: The core logic of the circuit is implemented using combinational circuits; The biggest drawback of asynchronous timing circuits is the tendency to produce glitches; Not conducive to device portability; Not conducive to static timing analysis (STA) and validating design timing performance.Synchronous Timing Circuits: The core logic of the circuit is implemented using various flip-flops; The main signals and output signals are driven by the clock edge triggering the flip-flops; Synchronous timing circuits can effectively avoid glitches; Beneficial for device portability; Beneficial for static timing analysis (STA) and validating design timing performance.

In synchronous design, stable and reliable data sampling must adhere to the following two basic principles:(1) Data input must be stable for at least the setup time of the sampling register before the valid clock edge arrives; this principle is referred to as satisfying the setup time principle;

(2) Data input must remain stable for at least the hold clock duration after the valid clock edge arrives; this principle is referred to as satisfying the hold time principle.

Considerations for Synchronous Timing Design:

Data conversion between asynchronous clock domains. Design methods for combinational logic circuits. Clock design for synchronous timing circuits.

The delay of synchronous timing circuits. The most commonly used design method for the delay of synchronous timing circuits is to use divided or multiplied clocks or synchronous counters to achieve the required delay. For relatively large and special timing requirements, a high-speed clock is generally used to generate a counter to produce delays; for smaller delays, a D flip-flop can be used to delay the signal by one clock cycle and achieve the initial synchronization of the signal with the clock. Additionally, there are behavioral-level methods to describe delays, such as “#5 a<=4’b0101;” which is commonly used in simulation test stimuli but will be ignored during circuit synthesis and will not have a delaying effect. The reg type defined in Verilog does not necessarily synthesize to a register. In Verilog code, the two most commonly used data types are wire and reg; generally, wire type data is implemented through combinational logic via wires, while reg type data does not necessarily use registers.

Common Design Concepts and Techniques

(1) Ping-pong operation; (2) Serialization/deserialization; (3) Pipelining; (4) Data synchronization between asynchronous clock domains. This refers to the issue of how to reliably exchange data between two clock domains that are not synchronized. There are mainly two cases of unsynchronized data clock domains:

Two domains have the same clock frequency but differ in a non-fixed manner, or differ in a fixed but unmeasurable manner, referred to as the same frequency but different phase problem.

Two clocks have completely different frequencies, referred to as the different frequency problem.

Two methods of asynchronous clock domain operation that are not recommended: one is to adjust sampling by adding buffers or other gates for delay; the other is to blindly use clock edges to adjust data sampling.

Basic Principles of Module Division:

(1) Use registers for the outputs of each sub-module in synchronous timing design (the principle of using registers to divide synchronous timing modules).

(2) Divide related logic and reusable logic into the same module (echoing the system principle).

(3) Separate logic with different optimization goals.

(4) Group logic that sends constraints into the same module.

(5) Independently divide storage logic into modules.

(6) Appropriate module size.

(7) The top-level module should ideally not perform logical design.

Considerations for Combinational Logic(1) Avoid combinational logic feedback loops (which can easily lead to glitches, oscillations, timing violations, etc.).

Solution:A. Remember that any feedback loop must include registers; B. Check the synthesis and implementation report warnings for feedback loops (combinational loops) and make corresponding modifications.

(2) Replace delay chains. Solution: Use frequency multiplication, division, or synchronous counters to achieve.

(3) Replace asynchronous pulse generation units (glitch generators). Solution: Use synchronous timing design pulse circuits.

(4) Use latches with caution.

Solution:A. Use complete if…else statements;

B. Check if there are any combinational logic feedback loops in the design;

C. For each input condition, design output operations, and set default operations for case statements. Especially in state machine designs, it is best to have a default state transition, and each state should also have a default operation.

D. When using case statements, especially in state machine designs, try to add synthesis constraint attributes to synthesize as fully conditional case statements.

Tips: Carefully check the synthesis report from the synthesizer; most synthesizers will report a “warning” for any synthesized latches, making it easier to identify any inadvertently generated latches through the synthesis report.

Considerations for Clock Design

Recommended Clock Design Method for Synchronous Timing Circuits:

Clocks are input through global clock input pins, adjusted and processed by the FPGA’s internal dedicated PLL or DLL for frequency division/multiplication, phase shifting, etc., and then driven to all registers and other module clock input terminals within the chip through the FPGA’s internal global clock wiring resources.

Five Basic Skills for FPGA Designers: Simulation, Synthesis, Timing Analysis, Debugging, Verification.For FPGA designers, mastering these five basic skills is part of the same process as effectively using corresponding EDA tools, with the correspondence as follows:

1. Simulation: Modelsim, Quartus II (Simulator Tool)

2. Synthesis: Quartus II (Compiler Tool, RTL Viewer, Technology Map Viewer, Chip Planner)

3. Timing: Quartus II (TimeQuest Timing Analyzer, Technology Map Viewer, Chip Planner)

4. Debugging: Quartus II (SignalTap II Logic Analyzer, Virtual JTAG, Assignment Editor)

5. Verification: Modelsim, Quartus II (Test Bench Template Writer) Mastering HDL language is not everything for FPGA design, but the influence of HDL language runs throughout the entire FPGA design process and is complementary to the five basic skills of FPGA design.

For FPGA designers, effectively using the “synthesizable subset of HDL language” can accomplish 50% of the FPGA design work—design coding.Mastering simulation, synthesis, and timing analysis as the three basic skills will help in learning the “synthesizable subset of HDL language” in the following ways:

1. Through simulation, you can observe the logical behavior of HDL language in FPGA.

2. Through synthesis, you can observe the physical implementation of HDL language in FPGA.

3. Through timing analysis, you can analyze the physical implementation characteristics of HDL language in FPGA.For FPGA designers, effectively using the “verification subset of HDL language” can accomplish another 50% of the FPGA design work—debugging and verification.

1. Build a verification environment to check the correctness of FPGA design through simulation.

2. Comprehensive simulation verification can reduce the workload of FPGA hardware debugging.

3. Combining hardware debugging with simulation verification methods can address issues not verified in simulation, ensuring that resolved issues do not reoccur in debugging, establishing a regression verification process that aids in maintaining FPGA design projects.The five basic skills of FPGA designers are not isolated; they must be used in combination to complete a complete FPGA design process. Conversely, completing a complete design process is the most effective way to practice these five basic skills. Once you have a preliminary understanding of these five basic skills, you can delve deeper into each one, and then apply the knowledge gained back into the complete design process. Repeating this cycle will gradually improve your design skills. By adopting this step-by-step, spiral approach, as long as you have received training to get started, you can self-learn and practice, and improve yourself. The books available on the market regarding FPGA design introduce each aspect separately to ensure structural integrity; although each aspect is deep, due to the lack of support from other related aspects, readers find it difficult to put it into practice. Only by reading the entire book can one gain a comprehensive understanding of FPGA design. Such books are not suitable as engineering training guides but can serve as reference books for advancing a specific aspect. For new employees, they often have a preliminary understanding of the overall FPGA design process, and some aspects of the five basic skills may be solid. However, due to deficiencies in one or several aspects, their ability to independently complete the entire design process is limited.

The purpose of onboarding training is to help them master the overall design process, cultivate the ability to self-acquire information, and through repeated training in several design processes, form a virtuous cycle of self-promotion and self-development. In this process, as their understanding of the breadth and depth of knowledge related to their work becomes clearer, the new employees’ confidence will gradually increase, and their personal development direction will become clearer, allowing them to actively participate in engineering projects.