100 Common Abbreviations in IC Design

English Abbreviation

Full English Name

Chinese Explanation

ADC

Analog to Digital Converter

Analog signal to digital signal conversion circuit

AHB

Advanced High Performance Bus

One of the AMBA bus specifications launched by ARM, mainly used for connecting high-performance modules (such as CPU, DMA, and DSP, etc.)

APR

Auto Place and Route

Automatic layout and routing, the main process of digital backend layout implementation

ARM

Acorn RISC Machine

The CPU processor commonly used in mobile chips from the UK ARM company, which is now basically adopted in low-power designs.

ASIC

Application Specific Integrated Circuit

Application-specific integrated circuit, the mainstream design process for chip design companies.

ATPG

Auto Test Pattern Generator

Test vector automatic generation tool, a common process in DFT.

AXI

Advanced eXtensible Interface

One of the AMBA bus specifications launched by ARM.

BE

Back End

Backend, referring to the backend design process in IC design.

BIST

Built-in Self-Test

Built-in test system, a common process in DFT.

CAD

Computer Aided Design

Computer-aided design, also a department in IC design companies that specializes in providing software automation.

CDC

Clock Domain Crossing

Asynchronous clock timing check, an important step in digital design.

COVERAGE

Coverage

Coverage, a common term in digital verification, mainly including code coverage and functional coverage.

CPLD

Complex Programmable Logic Device

Complex programmable device, similar to FPGA.

CTS

Clock Tree Synthesis

Clock tree synthesis, an important process in digital backend implementation.

DAC

Digital to Analog Converter

Digital signal to analog signal conversion circuit.

DC

Design Compiler

Synopsys’ digital synthesis tool.

DFT

Design for Test

A design method adopted to enhance chip testability, an important step in the digital IC process.

DMA

Direct Memory Access

Direct memory access.

DRAM

Dynamic Random Access Memory

Dynamic random access memory, the most common system memory.

DRC

Design Rule Check

Check whether the generated layout meets the design rules provided by the foundry, such as width, spacing, area, etc.

DSP

Digital Signal Processing

Digital signal processing module, algorithms in IC design companies often use.

DUT

Design Under Test

Design module under test.

DUV

Design Under Verification

Similar to DUT.

ECO

Engineering Change Order

In the later stages of a project, modifications to the chip design can only be made at the gate level.

EDA

Electronic Design Automation

Electronic design automation, a process that requires many EDA tools in IC design.

EEPROM

Electrically Erasable Programmable Read-Only Memory

Electrically erasable read-only memory.

ERC

Electronic Rule Check

IC design checks the layout for compliance with electrical rules after layout.

FE

Front End

Front end, referring to the front end design process in digital IC design.

FLASH

Flash EEPROM Memory

Flash memory, which has the characteristics of fast data reading like RAM and the erasability and non-volatility of EEPROM.

FM

Formal

Formal verification, comparing netlists with Verilog.

Foundry

Refers to the foundry business of chip manufacturing, responsible for producing completed chip designs.

FPGA

Field Programmable Gate Array

Field-programmable gate array, corresponding to the ASIC process.

FSDB

A common waveform file format in digital IC design.

FSM

Finite State Machine

Finite state machine in digital logic design.

FULLCHIP

Fullchip Level

Commonly used in digital front-end design and verification, referring to system-level and chip-level.

GDSII

File format for layout.

GLS

Gate Level Simulation

Refers to gate-level simulation in digital verification.

GPIO

General Purpose Input Output

General-purpose input/output, bus expander.

HDMI

High Definition Multimedia Interface

High-definition multimedia interface, a digital video/audio interface technology specification.

I2C

Inter-Integrated Circuit

IIC is a commonly used multi-directional control bus, simple, with only two wires.

IC

Integrated Circuit

Integrated circuit.

ICC

IC Compiler

Synopsys’ software for automatic place and route, widely used by many companies.

IEEE

Institute of Electrical and Electronics Engineers

Institute of Electrical and Electronics Engineers.

INNOVUS

Cadence’s digital layout implementation tool.

IP

Intellectual Property

Intellectual property, in digital IC design, the smallest design module is generally referred to as IP.

JTAG

Joint Test Action Group

Joint Test Action Group, an international standard testing protocol, commonly used for chip testing.

Layout

Layout, referring to the final layout generated for the chip, similar to design blueprints in the construction industry.

LPS

Low Power Simulation

Low power simulation, commonly used in low power design verification.

LSI

Large-Scale Integrated Circuit

Large-scale integrated circuit.

LUT

Look Up Table

Lookup table, used to store some data, essentially a type of RAM.

LVS

Layout versus Schematic

Check for consistency between layout and schematic after layout generation.

MCU

Microcontroller Unit

Microcontroller, the main control module.

MIPI

Mobile Industry Processor Interface

Mobile industry processor interface, an open standard and specification for mobile application processors.

Modelsim

Mentor’s digital front-end simulation tool, also known as QuestaSim.

MPW

Multiple Project Wafer

Multiple project wafer, refers to placing different chips of the same process on the same wafer, an effective way for small companies to save costs.

MSB

Most Significant Bit

The highest significant bit of multi-bit data, the corresponding concept is LSB.

NCSIM

Cadence’s digital front-end simulation tool.

NDR

Non-Default Route

Non-default routing rules, an important concept in layout implementation.

Netlist

Gate-level netlist, generally the netlist file generated by RTL code through synthesis tools.

NFC

Near Field Communication

A type of short-range wireless communication technology.

OCP

Open Core Protocol

An efficient, bus-independent, configurable, and highly scalable interface protocol.

PAD

Refers to the input/output ports of the chip.

PBA

Path-Based Analyze

Path-based timing analysis.

PCIe

Peripheral Component Interconnect Express

A standard for peripheral component interconnect, a common bus standard.

PD

Physical Design

Physical design, generally refers to the layout design of the digital backend.

PERL

A commonly used scripting language in digital IC design, very suitable for text processing.

PLL

Phase Locked Loop

Phase-locked loop, generally used in clock frequency multiplication circuits to generate clocks.

PT

Prime Time

Synopsys’ static timing analysis tool.

PV

Physical Verification

Physical verification required after digital layout implementation.

Python

A commonly used scripting language, now widely used in artificial intelligence and very popular.

R&D

Research and Design

R&D center.

RAM

Random Access Memory

Random-access memory.

REGRESSION

Regression testing, simply put, involves running all test cases repeatedly until there are no errors for a stable period.

RF

Radiation Frequency

Emission frequency, RF circuit.

RISC

Reduced Instruction Set Computer

Used in CPU for a reduced instruction set.

ROM

Read Only Memory

Read-only memory, which is non-volatile.

RTL

Register Transfer Level

Register transfer level, often refers to levels described using Verilog.

Shell

A commonly used scripting language in digital IC design, closely integrated with Linux.

SI

Signal Integrity

Signal integrity.

signoff

Acceptance mechanism, acceptance criteria.

SoC

System on Chip

System on chip, generally refers to larger scale chips, mostly containing CPUs/MCUs, etc.

SPEC

Specification

Specification, each engineer must write the corresponding spec.

SPI

Serial Peripheral Interface

Serial peripheral interface, a high-speed, full-duplex, synchronous communication bus.

SRAM

Static Random Access Memory

Static random-access memory.

STA

Static Timing Analysis

Static timing analysis, an important part of the digital IC design process.

SV

SystemVerilog

The mainstream digital verification language.

Tapout

Tapeout

Final layout file sent to the foundry for production.

TCL

Tool Command Language

Tool command language, commonly used scripting language in digital backend design.

tessent

Mentor’s DFT tool, with a high market share.

Testbench

Test platform, a platform used for testing in digital verification.

TTL

Transistor-Transistor Logic

TTL level standard, stipulates that +5V is equivalent to logic 1 and 0V is equivalent to logic 0.

UART

Universal Asynchronous Receiver/Transmitter

A common IP module.

USB

Universal Serial Bus

A high-speed bus protocol for connecting peripherals.

UVM

Universal Verification Methodology

The mainstream digital verification methodology, based on SystemVerilog.

VCD

Value Change Dump

A common waveform file format, detailed information but larger file size.

VCS

Synopsys’ digital front-end simulation tool.

Verdi

Synopsys’ digital front-end debugging tool.

VHDL

VHSIC (Very High Speed IC) Hardware Description Language

A hardware description language, similar to Verilog, now not widely used.

Vivado

Vivado

Integrated design environment released by Xilinx in 2012.

VLSI

Very-Large-Scale Integrated Circuit

Very-large-scale integrated circuit.