Summary of Using SPI with TMS320F2812

1. The SPI rate must not exceed 15M; exceeding this will result in serious bit errors.

2. If the reception method is interrupt-based, the SpicCR character length control bit determines the length of the interrupt. For a length of 8, with interrupt priority 1, an interrupt is generated for each byte received. For a length of 16, with interrupt priority 1, an interrupt is generated for every 2 bytes received.

3. Ensure that the polarity for master mode and slave mode is the same. The master mode samples on the rising edge and outputs on the falling edge. The slave mode should also sample on the rising edge and output on the falling edge. Otherwise, sampling data may be inaccurate.

4. Note that data written to SPITXBUF is left-aligned, while data read from SPIRXBUF is right-aligned. This issue is not prominent for 16-bit word lengths, but special attention should be given for word lengths below 16 bits. A common method is to perform a left shift operation.

5. Be aware of the usage of SPI FIFO. * r( U8 J8 g# ^

The biggest issue I encountered during debugging was data loss, which troubled me for several days. Later, I discovered that due to enabling the SPI FIFO enhancement feature, it was not possible to pause data transmission based on Spiaregs.SPISTS.bit.BUFFULL_FLAG. At this point, TXBUF is getting data from the TX FIFO. Writing to TXBUF in the program only writes to the transmit buffer, i.e., FIFO. According to the first-in, first-out principle, if you keep writing data to TXBUF, the FIFO will always retain your last written data, and BUFFULL_FLAG will not be set, leading to data loss. The correct method is to check the number of words in the SPI TX FIFO. If there are already 16 words in the sending FIFO, new data should not be sent at this time, and you should wait for the clock from the master on the SPI bus to move the data from TXBUF out, allowing the FIFO to automatically load one word into TXBUF before sending new data.