Occamy Processor Tape-Out: RISC-V Architecture with 216 Cores on GlobalFoundries 12nm Process

On May 9, news reported that the Occamy processor, sponsored by the European Space Agency and developed by researchers from ETH Zurich and the University of Bologna, has now been taped out.

The chip is based on the open-source RISC-V architecture and uses Chiplet technology, integrating two sets of 32-bit RISC-V cores totaling 216 cores, along with an unknown number of 64-bit Floating Point Units (FPU), and two 16GB HBM2e memory chips from Micron Technology.

Reports indicate that the processor’s cores are interconnected through an intermediary layer, allowing the two sets of CPUs to provide 0.75 FP64 TFLOPS of computing performance and 6 FP8 TFLOPS of computational capability. However, the European Space Agency and its development partners have not disclosed the power consumption of the Occamy. It has been reported that the chip employs passive cooling, indicating that it is a low-power processor.

One of the advantages of the Chiplet design is that it allows for the addition of smaller chips with other functionalities in future packaging, enhancing certain capabilities when necessary. Each Occamy chip contains 216 RISC-V cores and FPUs for floating-point operations, integrating approximately one billion transistors on a chip area of 73mm².

In comparison, Intel’s Alder Lake chip measures 163 mm². In terms of performance, NVIDIA’s A30 GPU has 24GB of HBM2 display memory, providing 5.2 FP64/10.3 FP64 Tensor TFLOPS and 330/660 INT8 TOPS.

Additionally, the Occamy CPU is primarily part of the European Space Agency’s EuPilot program and is one of the many chip options being considered for aerospace computing.

Currently, tests of the Occamy have shown that it can perform simulated operations on FPGA, and tests have been conducted on two AMD Xilinx Virtex UltraScale+ HBM FPGAs and the Virtex UltraScale+ VCU1525 FPGA.

Editor: Lin Zi, Source: technews