More than twenty years ago, the first high-voltage power module based on IGBT was launched. Today, it has become the industry standard for traction, motor drive, and renewable energy applications. With increasing demands for temperature, switching frequency, and higher power density, along with reduced system costs and improved reliability, a new solution has emerged. Hitachi has introduced a new industrial standard package named nHPD2. The nHPD2 package signifies the development of medium-voltage power converter designs.
The lowest stray inductance optimizes performance for SiC and Hitachi’s side-gate IGBT, enabling the market to choose the best solution for its specific design challenges, with ratings ranging from 1700V to 6.5kV.
nHPD2 Package
The nHPD2 series offers high-functionality half-bridge power modules integrated with temperature sensors and current detection terminals for optimal design performance.
This series provides dual package profiles suitable for various voltage and current ratings, maintaining the same footprint but with different heights, allowing for universal mechanical design and high levels of design repeatability for converters with different ratings. The compact shape, high power density convenience, and robust structure enable designers to achieve industry-leading converter designs.
Figure 1. nHPD2 Series Low (Left) and High Voltage Packages
Product Lineup
The nHPD2 series covers rated modules from 1700V to 6500V, with rated currents up to 1200A. All products in the LV package are now available as samples or in mass production, including:
• 1700V, 900A SiC – MBM900FS17AL
• 1700V, 1000A Si – MBM1000FS17G
• 1700V, 1200A Si – MBM1200GS17G2
• 3300V, 450A Si – MBM450FS33F
• 3300V, 600A SiC – MSM600FS33AL
• 3300V, 800A SiC – MSM800FS33AL
Figure 2. The World’s Highest Power Density nHPD2 3.3kV/800A, No SBR Diode
The target product lineup for HV packaging will begin rollout in the first half of 2019, as shown in Table 1.
Table 1. HV Target Portfolio
Latest Technology
Hitachi continues to apply the latest technological breakthroughs to the nHPD2 series to further expand performance ranges. The latest generation of side-gate IGBT, SiC, on-board temperature sensing, and copper sintering applications improve chip connections, ensuring optimal output power, energy loss, control, and lifespan.
Low Loss, High Controllability: Cost Advantages for Motor Systems
Compared to traditional trench IGBTs, side-gate IGBTs reduce energy loss and improve controllability. As shown in Figure 3a, loss trade-offs can be achieved by reducing the off-energy by 35% or the saturation voltage by 15%. The low gate charge reduces the load on the gate driver, and the low reverse recovery dv/dt and voltage overshoot allow for optimized switching to further reduce switching losses and can be easily integrated into converters, as shown in Figure 3b.
Figure 3. Side-gate IGBT Performance. Vce – Eff Trade-off (Left); Eon + Err – Recovery dV/dt – Motor Cost (Right)
In addition, the cost-effectiveness at the application level can consider two options. Instead of fully focusing on reducing system electrical efficiency (Eon + Err), there is an opportunity to weigh the full benefits of reducing motor or generator costs. Since the costs of motors and dv/dt filters can be associated with the level of isolation provided, relaxing the turn-off and recovery loss performance can lower the switching dv/dt (kV/us), thereby relaxing motor specifications and reducing costs. For example, based on an existing design with a motor isolated at 7kV/us, by accepting the status quo Eon + Err efficiency, the motor isolation can be downgraded to 2kV/us. By surveying common motor suppliers, we can transition from motors with enhanced winding isolation to motors with IEC/TS 60034-17 standard isolation. The cost advantage is 2.5 times, equivalent to a cost saving of 1.5k€ for a 30kW motor.
Further potential for reducing motor costs, the market-leading gate capacitance value (Qg) of the side-gate significantly reduces the power required to drive the gate. The typical GDU for a traditional IGBT half-bridge module rated at 1400A/1700V may consume 2x10W of power per GDU. The low Cres side-gate only requires 2x5W. In monetary terms, the cost reduction opportunities of GDU solutions may decrease by 50%.
The reduced reverse transfer capacitance (Cres) of side-gate IGBTs improves short-circuit performance while controlling better gate voltage and lower peak collector current. This provides a more robust power module under short-circuit conditions and reduces the current that must be dealt with in converter designs.
Longest Lifespan and Power Density
Using Hitachi’s proprietary copper sintering instead of the solder layer between the IGBT chip and the substrate significantly enhances the robustness of the module, improving the power cycling lifespan by ten times compared to standard solder. It also improves the thermal resistance of all chips and the I2t of the diode, providing the highest possible power density. This is particularly applicable to high-performance traction and wind power designs that require aggressive acceleration and high dynamic task profiles while ensuring overall reliability throughout the system’s lifespan. Figure 4 shows the sintered copper nanoparticles forming a strong chip connection joint.
Figure 4. Copper Sintering Mold Connection Process
Figure 5 shows a cross-sectional image after more than 400k cycles of power cycling, where Δj= 125K and Tjmax = 175°C, setting a new durability benchmark in the market for smaller targets, such as ΔTj= <100K and Tjmax = 150° C.
Figure 5. Cross-section After Power Cycling
Next Generation Silicon IGBT
nHPD2 is also optimized for the next-generation Hitachi silicon IGBT called dual-side gate. Hitachi’s primary strategy is to provide the best silicon IGBT and SiC MOSFET performance in the nHPD2 package, making our customer systems flexible and successful. The dual-side gate IGBT breaks the traditional performance limits of silicon. By applying dynamic carrier control, turn-off losses can be reduced by 45% compared to traditional trench IGBTs, and the Eoff-Vce(sat) trade-off approaches that of SiC MOSFETs while using standard silicon processes. To break the limits on IGBT loss reduction, it has been found that controlling carrier concentration before turn-off switching is very effective.
Figure 6 shows the simulated stored carrier density distribution and the performance of VCEsat and Eoff for high and low hole injection structures on the cutting-edge side-gate HiGT.
Figure 6. Simulated Carrier Density Distribution of Holes on Cutting-edge Side-gate IGBT
Adjusting the p-collector dose concentration allows for control of the conductivity modulation in the drift layer. However, due to the injected carriers from the MOS gate, the carrier density near the emitter surface cannot be effectively controlled. The accumulated carriers cause large turn-off currents during turn-off switching, which then limits further reductions in IGBT Eoff. As a method to break this limitation, we consider an ideal stored carrier profile, as shown in Figure 7.
Figure 7. Low Density Carrier Distribution, Low Loss Performance
In the on-state of the IGBT, a large amount of carriers should be stored for low VCEsat, while the carrier concentration stored near the emitter surface in the drift layer should be reduced before turn-off switching to facilitate the depletion of the drift layer, thus reducing low Eoff turn-off currents. By applying this idea, Eoff is reduced while maintaining low VCEsat, thereby breaking the traditional IGBT limitation: the trade-off performance between conduction and switching losses.
Figure 8 shows a schematic cross-section of the dual-side gate HiGT structure.
Figure 8. Concept and Structure of Proposed New Dual-side Gate IGBT
Driving two independent gates allows for effective controllability of conductivity modulation. In conductive mode, both side gates are used to inject a large number of electrons, thereby reducing VCE(sat). Before switching events, one of the side gates is turned off while the other gate remains on to reduce the amount of stored carriers, thus achieving faster switching during final turn-off. In addition to the critical dual-gate channel functionality, the advantages of standard side-gate structures also apply. This means low Miller capacitance, easy driving, and reduced short-circuit peak current, each contributing to the durability of the device and system.
Simulating the dual-side gate HiGT, Figure 9 shows the simulated stored carrier distribution in conductive mode (VGsE / VGcE = +15 V / + 15 V) and switching mode (VGsE / VGcE = +15 V / -15 V).
Figure 9. Simulated Stored Carrier Distribution of Dual-side Gate IGBT
In conductive mode, electrons are injected from both gates, and the stored carrier concentration near the emitter region is increased by the conductivity modulation effect produced. On the other hand, the carrier density stored in the emitter region is reduced through single-gate turn-off control. Figure 10 shows the simulated output characteristics of the dual-side gate HiGT.
Figure 10. Simulated Output Characteristics of Dual-side Gate IGBT
After trial production, the dual-side gate solution in conductive mode achieves a VCE(sat) of less than 2.7V, compared to the best trench gate in its class, MBN1800F33F (2.85V @ Tj = 150°C), although the conduction loss reduction of 6.0% is a secondary performance goal, reducing switching losses is the primary goal.
Next, we simulate the turn-off switching characteristics of the dual-side gate HiGT. Figure 11 shows the applied gate input signals and the obtained turn-off waveforms, with timing delays (tdelay) of the Gs and Gc signals.
Figure 11. Turn-off Drive Signal and Simulated Turn-off Waveform of Dual-side Gate IGBT
As tdelay increases, higher speed turn-off waveforms are obtained. This is a direct effect of using Gc control before the Gs off signal to reduce the stored carrier concentration. Table 2 summarizes the simulated stored carrier distribution after t delay, i.e., after applying Gc negative gate bias (-15V). It also highlights the impact on conduction losses during tdelay (Econd), turn-off switching losses (Esw), and total Eoff (Econd + Esw). As tdelay increases, a reduction in carrier concentration and an increase in Econd are observed, while showing a significant reduction in Esw. Therefore, the proposed dual-side gate HiGT’s Eoff is 31% lower than that of the traditional single-side gate HiGT, with a delay drive curve of 40μs.
Table 2: Simulated Eoff Dependence on tdelay
For information on the next-generation SiC “TED-MOS” and subsequent content, please click to read the original text.