On September 25, Xilinx held an online media sharing session to introduce how Xilinx’s FPGA products accelerate the development of emerging display panel technologies.
In recent years, as video content providers continue to launch higher quality content, and consumers persistently pursue better display effects, the upstream display panel technology has been continuously upgraded. In this context, display effects that support High Dynamic Range (HDR) technology are becoming a hot topic for manufacturers of display panels, smart TVs, smartphones, and more. During this process, Xilinx’s FPGA has provided significant assistance for the innovation of display panel manufacturers.
What is HDR?
HDR (High-Dynamic Range) images provide more dynamic range and image detail compared to ordinary images. It synthesizes the final HDR image using the best detail LDR (Low-Dynamic Range) images corresponding to different exposure times. It better reflects the visual effects in the real environment.
To present perfect HDR, two conditions must be met: wide color gamut and high brightness range.
The “snake chart” in the above image represents all the colors that the human eye can see. Currently, traditional HD televisions can only see the smallest triangle covered by Rec.709; however, 4K UHD televisions can cover a larger triangle range of DCI-P3; and 8K SHV can cover the range of the Rec.2020 triangle.
In terms of brightness, the range that the human eye can distinguish is from 0 to 10,000 nits, and beyond this range, it becomes meaningless to the human eye. The minimum brightness that ordinary LCD TVs can display is 0.1 nits, with a maximum brightness between 500 to 1000 nits.
The concept of HDR is to achieve a color gamut and brightness range close to what the human eye can cover. This involves using a camera to record the real natural color range and brightness that the human eye can perceive as accurately as possible, which is a process of photoelectric conversion, while the display needs to restore the real natural image recorded by the camera as accurately as possible, which is an electro-optical conversion process.
Therefore, HDR content production and display actually involve three factors: dynamic range, electro-optical transfer function (OETF/EOTF), and wide color gamut.
There are two commonly used HDR gamma curve standards in the industry: SMPTE 2084 which uses the Perceptual Quantizer (PQ) standard and Hybrid Log-Gamma (HLG) standard. PQ covers the entire brightness range by having most pixel bits represent lower brightness levels, which is a method of supplementing human eye sensitivity at lower detail levels.
Challenges HDR Brings to Panel Manufacturers
Although the HDR standard sets the same goals for content and displays, unfortunately, display technology is still far behind.
Bob Feng, the core market director of Xilinx Greater China, stated that most consumer LCD displays offer peak brightness of about 1000 nits, OLED offers about 800-1000 nits, quantum dots can achieve 1000 nits, while Micro LED can achieve 4000 nits, but all are much lower than the 10,000 nits brightness defined in HDR SMPTE2084.
Bob Feng
Director of Market and Business Development at Xilinx Greater China
Similarly, at low brightness levels, there are significant differences among different panel technologies. For example, for LCD display technology, it requires backlighting, and there are many types of backlighting sources. From the relatively simple edge-lit backlighting to direct-lit backlighting, then iterating to quantum dot backlighting and MiniLED backlighting, and then to stacked backlighting. Due to the presence of backlighting, the minimum brightness when displaying pure black is still close to 0.05-0.005 nits, which will significantly affect the realization of dynamic range.
While OLED and MicroLED are self-emissive and do not require backlighting, allowing them to achieve minimum brightness close to 0 nits (0.0001 nits). However, currently in large-size OLED TVs, LG is the only one that has a mature technology, while other panel manufacturers still face challenges in yield rates, and the cost of large-size OLED TVs is not very friendly to ordinary consumers. Micro LED, as a new technology, faces even greater challenges.
Similarly, in terms of color gamut range, most HDR displays do not meet the standards. Compared to the color gamut requirements of Rec. 2020 used in both HLG and PQ standards, most HDR displays only approach DCI-P3.
This means that while there are HDR contents that meet HDR production standards, various advertised HDR displays do not fully comply with HDR display standards. To solve this problem, further upgrades in display panel technology are needed, which may take time.
Therefore, how to improve the existing display panels’ reproduction of HDR content has become the primary issue facing panel manufacturers at this stage.
In response, many manufacturers have linked high dynamic range and wide color gamut together, forming a newer concept—3D color capacity, which Bob Feng vividly calls the “3D color bucket.”
Bob Feng stated that to best present HDR content with a larger color bucket to displays with smaller color buckets, an appropriate conversion or mapping process must be completed.
The effect of color capacity conversion depends on the HDR standard, display type, and display vendor. The HDR standard determines how to create deliverable content using selected gamma curves, maximum dynamic range, and color gamut, while the display type and vendor determine the actual representation capability.
Therefore, in different types of display panels (LCD/OLED/stacked/MicroLED) from different vendors, each needs to use specific color capacity mapping algorithms in its timing controller (TCON) to correctly match various color gamuts and contrast inputs, such as Hybrid Log-Gamma (HLG), HDR10, and Dolby Vision, thereby optimizing display effects to the maximum extent. Meanwhile, HDR content usually comes with different resolution and refresh rate requirements, greatly increasing the variety and bandwidth requirements of TCON input and output interfaces.
All of these make the conventional method of designing TCON using Application-Specific Integrated Circuits (ASIC) or Application-Specific Standard Products (ASSP) increasingly difficult, hindering the timely adoption of new innovative panels.
For example, if using ASIC or ASSP to design the panel’s TCON, panel manufacturers would need to design 12 different ASICs or ASSPs to match the four types of panels (LCD/OLED/stacked/MicroLED) and three resolutions (FHD/UHD/8K) (if considering different refresh rates, even more chips may be needed). Clearly, this presents not only a greater challenge for panel manufacturers but also requires a larger R&D investment, leading to higher overall costs. This also makes it difficult for manufacturers to focus on improving the yield and display performance of their panels.
Xilinx FPGA Assists Emerging Display Panel Innovation
In response to the challenges currently faced by panel manufacturers, Xilinx’s FPGA products provide a more flexible solution compared to ASIC or ASSP.
Since FPGA is a programmable logic device, it can adapt to more types of algorithms compared to ASIC or ASSP, which are fixed for specific algorithms. This means that a TCON based on an FPGA chip can meet the needs of various types of screens.
“Whether it’s LCD algorithms, OLED algorithms, stacked algorithms, or Micro LED algorithms, you can achieve this using the same FPGA chip. However, different resolutions and refresh rates require selecting different FPGAs. Therefore, different resolutions and refresh rates have significant differences in processing speed and bandwidth requirements,” Bob Feng from Xilinx Greater China explained. “For panel manufacturers, what might have required 12 ASICs or ASSPs to solve can now be done with just 4 FPGAs, greatly alleviating the burden on panel manufacturers. Choosing FPGA as TCON will become a very ideal choice for panel manufacturers.” (It is worth mentioning that Hisense’s stacked TV uses Xilinx’s FPGA as its TCON.)
In addition, FPGAs have other advantages, such as flexibility in video interfaces. Depending on the display vendor and type, the video output of TCON may vary among multiple signaling standards such as eDP, LVDS, RSDS, P2P, etc. Furthermore, TCON inputs are not limited to V-by-One interfaces, but can also reprogram HDMI or DisplayPort interfaces into the FPGA.
This architectural change allows TCON to connect directly with more network-friendly mobile SoCs (not just traditional TV SoCs). This improvement makes accessing the growing pool of HDR content easier and richer without increasing additional component costs. Moreover, mobile SoCs can even directly replace mainstream 4K TV SoCs, further simplifying circuits and reducing costs.
Bob Feng stated: “I believe the greatest feature and value of FPGA in TCON is that it is suitable for any screen, any interface, and any panel manufacturer.”
Currently, Xilinx has collaborated with Visionox to launch solutions based on Spartan 6, Kintex 7 VASSP, Kintex UltraScale KU060, and Kintex UltraScale KU115 for various panel manufacturers (including Samsung/LG/AUO/Innolux/BOE/CSOT) and different technology types (LCD/OLED/QLED) for FHD/4K@60FPS/8K@60FPS/8K@120FPS panels.
While FPGA has many advantages over ASIC in TCON design in the display panel field, it does not mean that FPGA can dominate everything and that ASIC has no role.
Bob Feng also admitted, “When panel technology is very mature and can be commercially mass-produced, choosing ASIC for TCON is appropriate.”
However, in Bob Feng’s view, currently, only LG’s technology for large-screen OLED is mature, while other panel manufacturers still cannot solve yield issues well, making it unwise to develop ASIC at this time. Additionally, new technologies such as stacked and MicroLED panels still face challenges in development or their commercial prospects are not yet clear. Choosing FPGA for TCON is the best choice in these circumstances.
“Whether for panel manufacturers or different screen technology types, the corresponding color capacity conversion buckets are different. All screens need to define a color bucket in advance, and then panel manufacturers need to design the screen according to that color bucket while simultaneously developing ASICs for the conversion algorithm for that color bucket. However, if there is a slight change in that color bucket during the screen design process, the originally designed algorithm may need to be changed, which is a disaster for the parallel ASIC development process. Therefore, developing ASIC before the corresponding screen technology is fully mature and commercialized will be very painful and difficult. FPGA can perfectly solve this problem during this process,” Bob Feng further explained.
Editor: Chip Intelligence – Langke Jian
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