Review of Previous Content
DDR Configuration of RZ/G2L
DDR Configuration of Renesas RZ/G2L MPU (1)
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Background Technology Introduction of DDR3 and DDR4
2.1
DDR3
#DDR3, as the third generation of double data rate synchronous dynamic random-access memory, holds an important position in the history of memory development. It employs an 8n prefetch architecture, allowing it to transfer data at eight times the data width per clock cycle, significantly enhancing data transfer efficiency.
In terms of operating voltage, the standard DDR3 operates at 1.5V, and with technological advancements, a low-voltage version, #DDR3L, has emerged, reducing the operating voltage to 1.35V. The transmission rate of DDR3 varies widely, ranging from 800Mbps in the early stages to 1600Mbps or even higher in later versions, meeting the performance requirements of various devices.
Regarding memory capacity, DDR3 chips have continuously increased in size, evolving from several hundred megabytes to several gigabytes, supporting higher system memory configurations. Its application fields are also extensive, with significant use in early desktop computers, laptops, and some embedded devices that do not have extremely high performance requirements.
2.2
DDR4
#DDR4 is a new generation of memory technology developed based on DDR3, bringing several significant performance improvements. It utilizes a 16n prefetch architecture, allowing it to transfer more data per clock cycle compared to DDR3’s 8n prefetch, theoretically doubling the data transfer rate.
The operating voltage has further decreased to 1.2V, which not only significantly reduces the power consumption of DDR4 but also minimizes heat generation, enhancing the stability and reliability of the memory. In terms of transmission rates, DDR4 starts at a rate of 2133Mbps, and with ongoing technological advancements, the rate continues to increase, meeting the high data transfer speed requirements of high-end servers, graphic workstations, and high-performance embedded systems.
DDR4 has also achieved breakthroughs in memory capacity, with single chips capable of reaching 16GB or more, providing a solid foundation for large-scale data storage and processing. Its advanced storage architecture and optimized electrical performance further enhance memory compatibility and stability.
2.3
DDR3L
DDR3L is the low-voltage version of DDR3, inheriting most of DDR3’s technical characteristics while optimizing power consumption. With an operating voltage of 1.35V, it reduces power consumption by approximately 10% – 15% compared to standard DDR3, which is significant for power-sensitive devices such as laptops, tablets, mobile devices, and some portable embedded devices, effectively extending battery life.
In terms of performance, DDR3L is comparable to DDR3 at the same frequency, meeting the needs of everyday office work, web browsing, and light gaming applications. Additionally, DDR3L maintains compatibility with DDR3 in terms of pin definitions and electrical characteristics, allowing device manufacturers to flexibly choose between standard DDR3 or DDR3L based on actual needs without making significant changes to the #hardware circuit, thus reducing product design and production costs.
2.4
Technical Characteristics and Differences between DDR3L and DDR4
|
Feature |
DDR3L |
DDR4 |
|
Operating Voltage |
1.35V |
1.2V |
|
Transmission Rate |
800–1333Mbps |
1333-1600Mbps (in RZ/G2L) Higher in actual applications |
|
Prefetch Mechanism |
8n Prefetch |
16n Prefetch |
|
Memory Capacity |
Single chip capacity is relatively small, generally in several GB |
Single chip capacity is larger, up to 16GB or more |
|
Power Consumption |
Lower, reduced compared to standard DDR3 |
Lower, further reduced compared to DDR3L, with higher energy efficiency |
|
Physical Design |
Uses traditional memory module design |
Optimized physical design, such as using fly-by topology to reduce signal interference and improve signal integrity |
|
Electrical Performance |
Signal stability is relatively weak at high frequencies |
Electrical performance optimized to better support high-speed data transmission |
|
Application Scenarios |
Devices with certain power consumption requirements but not extremely high performance needs, such as portable mobile devices and mid-range embedded systems |
Devices with high requirements for both performance and power consumption, such as high-end servers, graphic workstations, and high-performance embedded systems |
From the technical characteristics and differences, it can be seen that DDR4 outperforms DDR3L in terms of performance and power consumption, but its cost is relatively higher; while DDR3L has certain advantages in cost-effectiveness and power consumption control, making it suitable for cost-sensitive applications with moderate performance requirements.
3
DDR Configuration Tool Usage Process(Taking Renesas RZ/G2L as an example)
3.1
Introduction to Configuration Tool
The DDR configuration tool for RZ/G2L is officially named “RZG2L_G2UL_Five_A3UL_DDR_config_generation_tool_v3.0.1.xlsm”. It is an Excel-based tool that generates the code files required for initializing the DDR controller, namely param_mc.c and param_swizzle.c, through specific table settings and parameter configurations.
This tool is suitable for the RZ/G2L – LC – UL series MPU processors. Since these processors have the same DDR Memory controller and PYH, the configuration tool is the same. The latest version isv3.0.1.(You can copy the link below into your browser or scan the QR code to view)
v3.0.1
https://www.renesas.cn/zh/document/apn/pcb-design-guideline-ddr4ddr3l-including-ddr-config-generation-tool?r=1467981
In practical applications, the generated configuration files (param_mc.c and param_swizzle.c) are placed in different paths in the Flash – writer and trusted-firmware-a source projects, but the content is consistent. They need to be renamed according to the final selected topology’s connection and condition. For example, param_mc.c should be renamed to param_mc_{Connection#}_{Condition#}.c, and param_swizzle.c should be renamed to param_swizzle_{Topology#}.c.
In the Flash – writer source project, the file paths are
ddr/${PLAT}/param_mc{Connection#}_{Condition#}.c
ddr/common/param_swizzle{Topology#}.c;
In the trusted-firmware-a source project, the file paths are plat/renesas/rz/soc/${PLAT}/drivers/ddr/param_mc{Connection#}_{Condition#}.c
plat/renesas/rz/common/drivers/ddr/param_swizzle{Topology#}.c.
For more detailed usage instructions, please refer to the following websites:
Renesas Official Website
https://www.renesas.cn/cn/zh/products/microcontrollers-microprocessors/rz-mpus/rzg2l-getting-started
RZ Product WIKI Website
https://renesas.info/wiki/Main_Page
Conclusion
Stay tuned
The excitement is not over yet; in the next issue, we will delve into the DDR configuration tool usage process (taking Renesas RZ/G2L as an example), so stay tuned!
Need Technical Support?
If you have any questions while using Renesas MCU/MPU products, you can scan the QR code below or copy the URL into your browser to enter theRenesas Technical Forumto find answers or get online technical support.
https://community-ja.renesas.com/zh/forums-groups/mcu-mpu/
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