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The essence of FPGA is to design a chip, and its development is achieved through hardware description languages such as Verilog, compiled and synthesized through EDA tools into a download file, which is ultimately loaded into the FPGA device to complete the intended functionality. The hardware description language describes combinational logic and sequential logic circuits, where combinational logic consists of AND, NOT, OR circuits, and sequential circuits are triggered by flip-flops. In FPGA, combinational logic is implemented using lookup tables, thereby converting all digital circuits into lookup tables and registers, which form the basis of FPGA. Lookup tables are responsible for logic implementation, and registers store circuit states. Modern FPGAs also include RAM blocks for storing large amounts of data, saving chip area. The internal sequential circuits of FPGA require clock input, and since multiple types of clocks are usually needed internally, relevant clocks must be generated on-chip, making clock management units like DCM/PLL essential internal components. In addition, FPGAs also include I/O interfaces, which can be divided into ordinary I/O and high-speed I/O, along with various hard cores.
The English translation of FPGA is Field Programmable Gate Array, which is relative to ASIC. ASIC hardware can also be considered as a gate array, but it is a non-programmable device, with its functionality fixed after fabrication. However, the programmability of FPGA lies in its ability to re-download configuration files to change its internal functionality. Both have similar front-end development processes. The technology of FPGA is mainly monopolized by two major companies, ALTERA and XILINX.
(1) FPGA Architecture
In a complete embedded system, it is rare to have a single FPGA; it is usually completed by combining multiple devices, such as CPU + FPGA. Typically, it is an FPGA + ARM, where ARM is responsible for software configuration management and peripheral interface operations, and FPGA is responsible for large data computations, functioning as a dedicated co-processor for the CPU, often used to expand external interfaces. Common architectures include ARM + FPGA, DSP + FPGA, or network processors + FPGA, all forming the processing forms of high-speed embedded devices. In terms of achieving high-speed processing, the trend for CPUs is multi-core. Popular applications for FPGAs include:
1) Network storage devices
2) High-speed network devices
3) 4G communication devices: For signal processing in next-generation communication base stations, the architecture of FPGA + DSP arrays is a perfect match.
In summary, there is no perfect architecture, only suitable combinations.
(2) Device Interconnection
After determining the system architecture, the next step is the interconnection between the FPGA and various devices. Generally, the interconnection between the CPU and FPGA mainly depends on two factors:
1) The interfaces supported by the CPU
2) The interactive business
Typically, FPGAs support digital interfaces for connecting with CPUs, commonly including EMIF, PCI, Ethernet, DDR, etc. As a bus-type interface, FPGA usually connects as a slave device to the CPU, which acts as the master device accessing the FPGA through directly mapped addresses. Generally, bus access is divided into synchronous access and asynchronous access. The CPU manual will provide detailed timing control definitions for signal definitions, and the FPGA will implement corresponding logic based on these detailed specifications. The CPU will also set access timing, such as setting setup time, hold time, and maximum clock frequency. For bus-type access, data signals are usually tri-state, used for input and output, aiming to reduce the total number of external connections. The advantage of bus access is that it is directly mapped to the system’s address range, making access relatively intuitive, but the transmission rate is not high, primarily due to the following reasons:
1) Limited by bus access intervals, i.e., the idle state between two accesses
2) Does not support bidirectional transmission, and when FPGA actively initiates operations to the CPU, it can only use interrupt handling.
This bus-type operation characteristic allows it to be used for system management operations, such as configuring internal FPGA registers, configuring parameters needed during operation, and exchanging small amounts of information. These operations have suitable data amounts and bandwidth requirements, meeting the needs of ordinary embedded systems. For large data flow exchanges, dedicated bus interactions are generally used, characterized by supporting bidirectional transmission and faster bus transmission rates.
(3) FPGA Characteristics
The greatest characteristic of FPGA is its flexibility:
1) Flexibility of I/O, which can be composed of various interfaces to connect with various devices, supporting different electrical characteristics.
2) Flexibility of internal memory, which can generate various depths and widths of RAM and FIFO through IP generation tools.
3) Flexibility of logic, where internal logic can generate various types of IP.
(4) Architecture Design
1) Data-driven
For FPGA architecture design, the first consideration is performance, followed by interface design. General architecture design is implemented using a data flow-driven approach, typically applied in IP fields, storage fields, digital processing fields, and other large FPGA designs. This generally includes input interface units, main processing units, output interface units, and possibly auxiliary processing units and external storage units. These units usually adopt pipelined processing, i.e., once data is processed, it is packed and sent to the next level for processing. Multiple data input/output may occur, requiring internal architecture to implement data exchange.
2) Stability: The design must be able to operate normally.
3) Clock domain reset: Reset is generally performed using asynchronous reset and synchronous release methods.
4) Parallelism and reuse: Parallelism can improve processing speed, while reuse can save resources. The final design depends on the trade-off between design processing capability and logic quantity.
5) Pipelined processing: Simplifies design; optimizes timing. However, pipelined design cannot handle designs with feedback; imposing pipelined design may waste logic and design.
(5) Common Internal Resources in FPGA
1) FIFO Design: A commonly used internal resource in FPGA, most commonly associated with asynchronous clock domain partitioning and buffering data, but not limited to this. Simplifying design, reducing coupling, and fixing input/output interfaces are all benefits of using FIFO.
2) RAM: Typically instantiated RAM can be of two types: BLOCK RAM and distributed RAM, where the former provides larger storage capacity and the latter provides smaller storage capacity.
(6) Coding Principles
1) Comments: Good code must have comments, which should at least include file comments, port comments, and functional statement comments. Good comments can enhance code readability and maintainability.
2) Statements: The written statements must be synthesizable; in FPGA design, they are either sequential logic or combinational logic. Combinational logic takes effect immediately, while sequential logic takes effect at the next clock edge.
3) Blocking and non-blocking assignments: Generally, combinational logic uses blocking assignments, while sequential logic uses non-blocking assignments.
4) Avoid generating latches: Latches are most easily generated in always(*) modules; all branch conditions must be described and assigned, and the default state in state machines should not be forgotten.
(7) Interface Design
When designing, an interface module is needed, and the following questions must be clarified:
1) Is it a synchronous or asynchronous interface?
2) What signals are there, and what are their functions?
3) What are the timing relationships between the signals?
4) What is the efficiency of the transmission?
The answers to these questions are generally provided in the datasheet. When designing an interface module, it must connect with other hardware circuits. If the external connection interface is a bus interface, it must include at least the following signals:
1) Address: The maximum address space supported, whether data and address are reused.
2) Data: Generally, read and write data reuse the same interface.
3) Read and write commands.
4) Whether burst transmission is supported.
5) Synchronous or asynchronous.
6) The phase relationship between control signals and the requirements for setup time and hold time.
(8) Learning Bus Design
In the PC era, Microsoft and Intel monopolized the market, while in the mobile internet era, the most promising players are Google’s Android system and ARM chips. As a result, the AMBA bus standard for on-chip interconnections in ARM processors has become the most widely used standard in the industry.
The AMBA bus is actually a collection of three standards: AHB, ASB, and APB. ASB has gradually been replaced by AHB, and now the most widely used are AHB and APB buses, along with the latest extended AXI bus. The following figure shows the application scenario of AHB and APB in an embedded system.
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