Corrector: TinyCorrect v0.1-rc3 – [epw]Title: [A First Look at RISC-V Virtualization from an Embedded Systems Perspective][001]Author: Bruno Sá, José Martins, Sandro Pinto@March 27, 2021Translator: trueptolemy [email protected]: 2022/08/11Revisor: Falcon [email protected], Walimis [email protected]: RISC-V Linux Kernel AnalysisSponsor: PLCT Lab, ISCAS

This week begins the serialization of the RISC-V Virtualization series translations and articles, expected to last 3-4 months. Remember to bookmark and share + follow, write articles to receive subsidies: gitee.com/tinylab/riscv-linux

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A Comprehensive Overview of RISC-V Virtualization from an Embedded Systems Perspective

Abstract—This article describes the first public implementation and evaluation of the latest version of the RISC-V hypervisor extension (H-extension v0.6.1) specification in a Rocket chip core. To perform a meaningful evaluation for modern multi-core embedded and mixed-criticality systems, we have ported Bao, an open-source static partitioning hypervisor, to RISC-V. We have also extended the RISC-V platform-level interrupt controller (PLIC) to enable direct guest interrupt injection with low and deterministic latency and we have enhanced the timer infrastructure to avoid trap and emulation overheads. Experiments were carried out in FireSim, a cycle-accurate, FPGA-accelerated simulator, and the system was also successfully deployed and tested in a Zynq UltraScale+ MPSoC ZCU104. Our hardware implementation was open-sourced and is currently in use by the RISC-V community towards the ratification of the H-extension specification.

Keywords Virtualization, RISC-V, H-extension, Hypervisor, Partitioning, Mixed-criticality, Embedded Systems.

Introduction

This article is a translation of the paper “A First Look at RISC-V Virtualization from an Embedded Systems Perspective”.

This paper was first publicly released on [arxiv][001] on March 27, 2021, and later published in the IEEE Transactions on Computers. This article is based on version 2 of the paper published on arxiv.

This paper introduces the implementation of the RISC-V virtualization extension (H-extension) version 0.6.1 on the Rocket chip. This is the first implementation of the H-extension and is currently the only open-source implementation.

As of now, hardware implementations supporting the H-extension include the Rocket chip (FPGA implementation), De-RISC’s [RV64GC][002], and SiFive’s [P650][012]. Among them, RV64GC’s support for the H-extension was announced on April 28, 2021, which is an FPGA implementation, but the relevant implementation details have not been made public. The P650 is the first commercially announced chip to support the H-extension, released on December 2, 2021, and is not yet on the market.

This article mainly contains the following three parts:

1. Introduction to H-extension and Rocket chip (Sections 1 to 3);
2. Enhancements in interrupt virtualization on the Rocket chip and the porting of the Bao hypervisor to RISC-V (Sections 4 to 5);
3. Performance evaluation and discussion of the H-extension (Sections 6 to 9).

RISC-V Virtualization Support

The RISC-V privilege architecture [15] features originally three privilege levels: (i) machine (M) is the highest privilege mode and intended to execute firmware which should provide the supervisor binary interface (SBI); (ii) supervisor (S) mode is the level where an operating system kernel such as Linux is intended to execute, thus managing virtual-memory leveraging a memory management unit (MMU); and (iii) user (U) for applications.

The modularity offered by the ISA allows implementations featuring only M or M/U which are most appropriate for small microcontroller implementations. However, only an implementation featuring the three M/S/U modes is useful for systems requiring virtualization.

The ISA was designed from the ground-up to be classically virtualizable [18] by allowing to selectively trap accesses to virtual memory management control and status registers (CSRs) as well as timeout and mode change instructions from supervisor/user to machine mode.

For instance, mstatus’s trap virtual memory (TVM) bit enables trapping of satp, the root page table pointer, while setting the trap sret (TSR) bit will cause the trap of the sret instruction used by supervisor to return to user mode. Furthermore, RISC-V provides fully precise exception handling, guaranteeing the ability to fully specify the instruction stream state at the time of an exception.

In this work, we share our experience while providing the first public hardware implementation of the latest version of the RISC-V H-extension in the Rocket core [16]. While the specification is intended to fulfill cloud and embedded requirements, we focused our evaluation on modern multi-core embedded and mixed-criticality systems (MCS). In this context, we have ported Bao [2], a type-1, open-source static partitioning hypervisor, to RISC-V.

In the spirit of leveraging the hardware-software codesign opportunity offered by RISC-V, we have also performed a set of architectural enhancements in the interrupt controller and the timer infrastructure aiming at guaranteeing determinism and improving performance, while minimizing interrupt latency and inter-hart interference.

The experiments carried out in FireSim [17], a cycle-accurate, FPGA-accelerated simulator, and corroborated in Zynq UltraScale+ MPSoC ZCU104, demonstrate significant improvements in performance (<1% overhead for hosted execution) and interrupt latency (>89% reduction for hosted execution), at a fraction of hardware costs (11% look-up tables and 27-29% registers).

We released our hardware design as open source and the hardware is currently being used as a reference implementation by the RISC-V International to ratify the H-extension specification.

In summary, with this work, we make the following contributions: the first public and open source implementation of the latest version of the RISC-V H-extension (v0.6.1) in a Rocket Chip core (Section 3); a set of hardware enhancements, in the platform-level interrupt controller and the architectural timer infrastructure, to tune virtualization support for embedded and mixed-criticality requirements (Section 4); the port of the open source Bao hypervisor for RISC-V (Section 5); the development of an open source ad-hoc testing framework that enable the raw functional validation of fine-grain features of the hypervisor specification (Section 6.1); the first public and cycle-accurate evaluation of the H-extension in a RISC-V core. We focused on hardware costs, performance overhead, inter-VM interference, and interrupt latency (Section 6);

In conclusion, we have presented the first implementation of the RISC-V H-extension in a real RISC-V core, i.e., Rocket core. We also proposed a set of hardware enhancements to the interrupt controller and the timer infrastructure aiming at tackling mixed-criticality systems requirements of minimal latencies, determinism and predictability. Our results demonstrated that the H-extension introduces a reduced performance penalty, but without additional hardware support interference and interrupt latency can impose a prohibitive cost for MCSs. Our proposed architectural enhancements considerably minimize these effects, by reducing interrupt latency and interference by an order of magnitude. Lastly, we discussed identified gaps existing in RISC-V with regard to virtualization and we outlined internal ongoing efforts within RISC-V virtualization. Our hardware design was made freely available for the RISC-V community and is currently the single reference implementation available to ratify the H-extension specification.