Three Secrets to Maximize Efficiency in ARM Cortex M3/M4 MCU Designs

Most applications using Cortex-M3/M4 MCUs are portable and powered by batteries or energy harvesting systems. Therefore, most of the concepts discussed in this article involve how to reduce overall system energy consumption. However, in many cases, these energy-saving technologies are also powerful tools for processor application design, providing more cost-effective solutions, greater design redundancy for upgrades and new features, and helping products stand out in a competitive market with their performance and features.

Quick Tip: Comparison of Cortex-M3 and Cortex-M4

The guiding principle behind the Cortex-M3 architecture is to design a processor that meets the cost-effectiveness of applications while providing high-performance computing and control. Similar applications include automotive body systems, industrial control systems, and wireless network/sensor products. The M3 series introduces several important features to the 32-bit ARM processor architecture, including: Non-maskable interrupts; High determinism, nested, vectored interrupts; Atomic bit operations; Optional memory protection (MPU).

In addition to excellent computing performance, the advanced interrupt structure of the Cortex-M3 processor ensures that the system responds quickly to real-world events while still providing extremely low dynamic and static power consumption.

Let’s Get to the Point

SWO Interface Saves I/O Pins and Accelerates Debugging

In addition to traditional Serial Wire Debug (SWD) functionality, ARM Cortex-M based MCUs can also provide an instruction trace interface through its single-pin Serial Wire Output (SWO), as shown in Figure 1. This interface can directly pass “printf” formatted debugging information to application code. SWO allows debugging information to be browsed directly in any standard IDE. Additionally, this information can also be viewed using standalone SWO monitors (such as Segger’s J-Link SWO Viewer software or Silicon Labs’ energyAware Commander). Since SWO output is built into the core hardware itself, it is an inherent advantage of the Cortex-M core.

SWO does not occupy any UART interfaces of the MCU, which may have already been allocated to the application.

Three Secrets to Maximize Efficiency in ARM Cortex M3/M4 MCU DesignsFigure 1 Dedicated ARM Cortex SWO Interface Saves I/O Pins and Accelerates Debugging

SWO-based debugging has another important advantage: it allows the microcontroller to maintain a valid debug connection when entering the lowest sleep mode, whereas in most cases, traditional debug connections cannot function properly at this time. SWO’s instruction tracing can also be used to track the program counter to help the IDE calculate the time consumed by various functions of the program. These statistics can be combined with current measurements to help developers fine-tune design power consumption.

Currently, some vendors are beginning to recognize this advantage, and some manufacturers have incorporated power mode and current measurement hardware into their development platforms for this purpose. For example, Silicon Labs’ EFM32 Gecko MCU starter and development kits include power measurement outputs and can be paired with the program code tracing functionality in the energyAware Profiler tool. Figure 2 shows how designers can accurately identify which program function block consumes the most energy and quickly debug other energy-related issues.

Three Secrets to Maximize Efficiency in ARM Cortex M3/M4 MCU DesignsFigure 2 Software and Hardware Tools Accurately Locate the Most Energy-Consuming Functions Without an Oscilloscope and Multimeter, Quickly Troubleshooting Issues

Smart Sleep Saves Every Micro-Watt

The Sleep-on-Exit feature of ARM Cortex-M processors (entering sleep directly after interrupt completion) is another “two birds with one stone” functionality that saves both CPU cycles and energy consumption. This is particularly useful in interrupt-driven applications, as the processor spends most of its time either executing interrupt handling or sleeping between interrupt events. When entering the Interrupt Service Routine (ISR), the MCU must spend several instruction cycles to stack the current thread state, and then restore the original thread state upon exiting the interrupt handling, that is, “unstacking”. When an application requires the processor to enter sleep mode directly after exiting the ISR, traditional MCUs still need to restore the previously stored state information before the thread code can allow the MCU to enter sleep mode. Similarly, when the next interrupt wakes the MCU, its state must be stacked again.

However, when enabling the Sleep-on-Exit feature on ARM Cortex-M microcontrollers, the MCU will directly enter sleep mode after interrupt handling, without first returning to the original thread (see Figure 3). This keeps the processor in interrupt status, as it eliminates the wake-up and unstacking process, thus saving many precious machine cycles. Eliminating the unstacking process saves both time and energy consumption; otherwise, energy would be wasted on unnecessary instruction cycles, including the code that traditional MCUs use to manage the stack during sleep and wake cycles. Furthermore, when the processor is awakened by a Halt Debug Request, the unstacking process will be performed automatically.

Three Secrets to Maximize Efficiency in ARM Cortex M3/M4 MCU Designs

Three Secrets to Maximize Efficiency in ARM Cortex M3/M4 MCU DesignsFigure 3 ARM Cortex-M’s Sleep-on-Exit Function Reduces Power Consumption by Avoiding Unnecessary Code Execution and Reducing Unstacking Operations

ARM Cortex-M4 Runs Faster and Has Lower Sleep Power Consumption

Like many MCUs, Cortex-M3/4 processors can typically save energy in interrupt-driven applications by using high clock rates. If the processor spends most of its time in sleep mode, this seemingly counterintuitive but commonly adopted energy-saving strategy works well, as the energy saved from reduced runtime far exceeds the slightly higher operating current. Simply put, spending 10% more energy can save 20% of time, resulting in overall energy savings.

This technology can be applied to any Cortex-M series processor, and applications involving intensive computation tasks can also benefit from the additional capabilities of the Cortex-M4 processor. Its single-cycle DSP instructions and optional floating-point accelerator can greatly reduce the number of execution cycles required for functions such as digital signal processing, filtering, analysis, or waveform synthesis.

The aforementioned energy-saving features can also bring other advantages. For example, in applications such as ultrasonic/acoustic water meters, which must operate for many years on small battery power, the MCU needs to stay in sleep mode as long as possible. In addition to helping reduce MCU wake-up time, the Cortex-M4 DSP and floating-point arithmetic instructions can also use mature filtering functions to extract the required information from inexpensive acoustic sensor outputs, thus avoiding the need for expensive ultrasonic flow sensors. In this application example, the peripherals of the Wonder Gecko MCU can also serve as an analog state machine, waking the Cortex-M4 processor only when necessary.

While not exhaustive, these various tips and tricks should provide good ideas for leveraging some of the lesser-known features of the Cortex-M series in your next design.

Three Secrets to Maximize Efficiency in ARM Cortex M3/M4 MCU Designs

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