This article is reprinted from「Quantum Bit」
After the release of DeepSeek V3.1, an official message caused a stir in the entire AI community:
New architecture, next-generation domestic chips, in less than 20 words, contain a huge amount of information.
Domestic chip companies’ stock prices also surged, with Cambricon rising nearly 14% in early trading today, making it the top market value on the Sci-Tech Innovation Board.
The semiconductor ETF also rose 5.89% in just half a day.
What exactly is this UE8M0 FP8? What does the next-generation domestic chip refer to?
Let’s start with the concept of UE8M0 FP8.
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01
What is UE8M0 FP8?
The concept of “UE8M0 FP8” can be explained by breaking it into two parts. The front part, UE8M0, is the “scaling factor” in the MXFP8 path.
MXFP8 is an 8-bit micro-scaling block format defined in the “Microscaling (MX) Formats Specification v1.0” released by the Open Compute Project in 2023.
The Open Compute Project is an open-source hardware collaboration initiative launched in 2011 by Facebook (now Meta) in conjunction with Intel, Rackspace, and others, aimed at improving industry efficiency through shared data center and server designs.
Its member lineup is quite strong, including Microsoft, Google, Amazon, AMD, NVIDIA, and domestic companies like Alibaba, Tencent, and Baidu.
Returning to MXFP8, it is built on the basis of FP8, which is a coding method that compresses conventional floating-point formats to 8 bits.
The core idea of MXFP8 is to first cut the tensor into fixed-length “blocks,” then assign a power of 2 as the “scaling factor” for each block, dividing all numbers within the block by this coefficient before writing them as FP8.
This block-level (rather than tensor-level) scaling allows MXFP8 to retain the 8-bit width while expanding the usable dynamic range by dozens of times.
Source: NVIDIA Technical Blog
The “scaling factor” here also consists of 8 bits, which include the sign bit, exponent bit, and mantissa bit. Developers can allocate these 8 bits among these three different types.
The sign bit only distinguishes between positive and negative; if present, it occupies one bit, otherwise it does not occupy any. The “U” in UE8M0 indicates that it is unsigned (signed can be represented as “S” or omitted).
The “E” and “M” represent the number of bits allocated to the exponent and mantissa, respectively. E8M0 means all 8 bits are allocated to the exponent.
Other commonly used formats include E4M3 and E5M2 (the body part outside the scaling prefix is often represented in these two formats), all of which include a sign bit, with the remaining 7 bits allocated between the exponent and mantissa.
The FP8 GEMM kernel DeepGEMM, which was previously open-sourced by DeepSeek, already supports UE8M0, but this project is mainly adapted for NVIDIA chips and the CUDA ecosystem.
So, what are the benefits of using this exponent-only representation for the scaling factor?
First, since UE8M0 does not contain mantissa and sign bits, when the processor restores data based on the scaling factor, it only needs to multiply by the corresponding power of 2, which means simply shifting the exponent, without needing floating-point multiplication, normalization, or rounding logic, thus shortening the critical path of the clock.
Moreover, the dynamic range of UE8M0 covers from 2^(−127) to 2^128, and its exponent table can easily accommodate this span, providing ample space for subsequent block scaling.
Additionally, UE8M0 can solve the problem of single-scale FP8 being unable to account for both large and small values, leading to overflow or being compressed to 0. By using UE8M0 as the block scale, the error rate curve drops from the entire curve to a much lower horizontal line, significantly reducing information loss while maintaining 8-bit tensor precision.
Source: NVIDIA Technical Blog
Now that we understand the benefits of UE8M0 FP8, we can explain why it is more suitable for the “next-generation domestic chips”.
Most of the domestically produced AI accelerators that have already been mass-produced still use the FP16/BF16 + INT8 computing path and have not integrated complete FP8 multiply-accumulate units like E4M3/E5M2.
However, the new domestic chips such as Moore Threads MUSA 3.1 GPU and Chipone VIP9000 NPU, which will debut in the second half of 2025, have already listed “native FP8” or “Block FP8” support in their promotional materials and have jointly verified the UE8M0 format with DeepSeek, Huawei, and 15 other manufacturers.
Although the next-generation domestic chips are already preparing for FP8, the HBM/LPPDDR bandwidth still has a significant gap compared to top chips.
UE8M0 allows a group of 32 FP8 data to only add an 8-bit scaling prefix, saving 75% of the traffic compared to the traditional 4B (32-bit) FP32 scaling. This space-saving measure is seen as an important optimization direction for the next-generation architecture.
02 Which domestic chip has DeepSeek optimized for?
After understanding what UE8M0 FP8 is, netizens began to speculate:
Which domestic chip is DeepSeek referring to?
With the official intentionally keeping it a mystery, people had to first focus on the eight manufacturers that were the first to be “DeepSeek large model compatible”.
Source: China Academy of Information and Communications Technology Official WeChat
Among them, the “top seed” that everyone is optimistic about is Cambricon, and the market reaction is quite direct —
As of today at 10:25, Cambricon’s stock surged nearly 14%, with a total market value exceeding 494 billion yuan, surpassing SMIC to become the top on the Sci-Tech Innovation Board(actual value subject to the latest data).
The reason is simple: the company’s MLU370-S4, Siyuan 590, and the latest 690 series chips all support FP8 computation and have been relatively advanced in architecture design and low-precision computation optimization.
For similar reasons, companies like Haiguang, Muxi, Zhonghao Xinying, and even Moore Threads, which is not on the list, have also been named by netizens:
- Haiguang: Its Deep Computing No. 3 DCU supports FP8 computation and has room for further optimization;
- Muxi: The Xiyun C600 released in July this year also supports FP8 precision computation;
- Zhonghao Xinying: Its “Shan” TPU AI chip supports FP8 precision;
- Moore Threads: As one of the few domestic GPU manufacturers that natively support FP8, its flagship product MTT S5000 supports FP8 precision computation.
Meanwhile, some manufacturers that are very likely to “soon adopt FP8” also appeared in various lists.
For example, Huawei Ascend, although the Ascend 910B and 910C do not currently support native FP8, the official roadmap has stated “native FP8 by Q4 2025”, so it is expected that the 910D (possible naming) to be launched in 2026 will likely be the so-called “next-generation chip”.
In addition to these, a large number of chip manufacturers’ names have appeared in the discussions, creating an unprecedented scene.
Although there is no final conclusion after all the speculation, it does not prevent the market from responding enthusiastically. According to the latest news, today the concept of domestic chips opened collectively high, with the Sci-Tech Innovation 50 index rising 3%, reaching a nearly three-and-a-half-year high, and the chip industry chain collectively strengthened.
So, why is everyone celebrating? What does it mean for these domestic chips to support UE8M0 FP8?
Based on current statements from various parties at home and abroad, everything can be summarized in one sentence:
This represents that domestic AI is moving towards a stage of software-hardware synergy, which can substantially reduce dependence on foreign computing power from NVIDIA, AMD, etc.
The logic here is simple and clear: it is precisely because of the advantages of the UE8M0 FP8 precision format (smaller bandwidth, lower power consumption, higher throughput) that the same hardware can run larger models in the future, thus significantly enhancing the “cost-performance ratio” of domestic chips.
In other words, these domestic chip manufacturers will have a competitive advantage, which is undoubtedly a positive development.
On the other hand, by modifying the precision format, DeepSeek is actively aligning with the optimal performance points of domestic chips, and this model of software-hardware synergy undoubtedly pulls domestic chips into a unified ecological coordinate system.
This is similar to the “Wintel Alliance” of the past — Microsoft and Intel built an ecological moat in the personal computer field through deep technical binding, only now it has changed to DeepSeek and domestic chip manufacturers.
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