RK3588 is a high-performance application processor chip from Rockchip, which adopts ARM’s big.LITTLE architecture, combining four high-performance Cortex-A76 cores and four efficient Cortex-A55 cores.
The big.LITTLE technology intelligently switches between high-performance “big cores” and low-power “LITTLE cores” to achieve the best balance of performance and energy efficiency under different workloads.
RK3588 supports HDMI 2.1 with a maximum resolution of 8K@60Hz, and is backward compatible with HDMI 2.0 and HDMI 1.4. In HDMI 2.1 mode, RK3588 operates in FRL mode, while in HDMI 2.0 and lower modes, it operates in TMDS mode.
FRL mode: In the traditional TMDS architecture, a separate channel is used to transmit the clock (TMDS: 1 group of clock, 3 groups of data), but in the FRL architecture, the clock is embedded in the data channel, and at the Sink end (receiver, such as a TV or monitor), the clock is recovered through clock recovery.
FRL mode (Fixed Rate Link) only has 3 lanes and 4 lanes working modes.
In 3 lanes working mode, it supports two rates of 3 Gbps and 6 Gbps.
In 4 lanes working mode, it supports four rates of 6/8/10/12 Gbps (the rate of each lane, i.e., the maximum bandwidth of HDMI 2.1 FRL can reach 48 Gbps).
TMDS mode (Transition Minimized Differential Signaling) is a technology that minimizes transmission differential signals, with a pull-up voltage of 3.3V for differential signals, a port (Sink end) impedance of 50 ohms, a single-ended signal of 400~600mV, nominally 500mV, and a differential signal logic swing between 800-1200mV, with the bias voltage provided by the Sink end, with a DC bias voltage of 2.8V. That is, the source end (RK3588, HDMI output end) generates a current source of 10mA, and the sink end is pulled up to 3.3V 50 ohms.
Figure 1 TMDS/FRL differential pair conceptual schematic
Figure 2 single-ended differential signal
Figure 3 differential signal
RK3588 HDMI 2.1 schematic reference design:
Figure 4 demo reference schematic
In HDMI 2.1 mode, HDMI0_TX_ON_H is configured to low level, and Q5000, Q5001, Q5002, Q5003 are off.
In HDMI 2.0 and lower modes, HDMI0_TX_ON_H is configured to high level, and Q5000, Q5001, Q5003 are on, forming a DC bias of about 3V with a 590 ohm resistor to ground and a 50 ohm pull-up at the sink end.
The roles of 499R and the MOSFET are to provide bias voltage when in HDMI 2.0 mode.
If only HDMI 2.0 and lower modes are needed, 499R and the MOSFET cannot be omitted, and it is necessary to ensure that the transistor is off when the device is powered off.
Because HDMI CTS TestID7-3 TMDS Voff testing requires that when the DUT is powered off, the Voff voltage must be within AVcc+-10mV, otherwise this test item cannot pass.
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