Note: The previous articles introduced the simplicity and practicality of PlutoSDR, and this article serves as an introduction to PlutoSDR, which should have been placed in the first post; this article is the 0th article!
ADI Pluto is an Active Learning Module launched by ADI, which mainly includes three devices: ADALM1000, ADALM2000, and ADALM-PLUTO. The first two devices are more focused on basic circuit measurements, while ADALM-PLUTO is more focused on software-defined radio.
PlutoSDR has independent receiving and transmitting channels and can operate in full-duplex mode. The active learning module can generate or capture RF analog signals at a maximum of 61.44MSPS across a frequency range of 325 MHz to 3800 MHz. PlutoSDR is very small and can fit in a shirt pocket, fully self-sufficient and powered by USB with default firmware. Since PlutoSDR starts via the libiio driver, it supports OS X®, Windows®, and Linux®, allowing students to learn and explore on multiple devices.
Pluto is an SDR architecture based on FPGA, essentially a packaged version of Zynq FPGA + AD936X, many commercial SDR versions we see are also based on this platform. However, directly getting into FPGA and AD9361 development is relatively difficult for many developers, and there is not much necessity for algorithm development and learning. The firmware of Pluto is also open-source.
https://github.com/analogdevicesinc/plutosdr-fw
The Pluto device from ADI is indeed a good learning platform, during development, FPGA development is not required, and it can be called using the Libiio components developed by ADI. As shown in the above image, through the LibIIO component, the underlying SDR resources can be directly called, making development much easier. The upper layer can be developed using languages and platforms like C, Matlab, etc.
The ADALM-PLUTO Active Learning Module is based on AD9363, equipped with one receiving channel and one transmitting channel that can work in full-duplex mode. The module can generate and measure RF analog signals in the frequency range of 325MHz to 3800MHz at a sampling rate of up to 61.44MSPS and a bandwidth of 20MHz. PlutoSDR is compact and can easily fit into a pocket or backpack, is flexible in use, and is powered by a USB port with default firmware. The module supports OS XTM, WindowsTM, and LinuxTM, allowing users to learn and explore RF systems on different devices at different times.
Why is it called “Pluto”
In geography, the celestial body “Pluto” is a dwarf planet, which is similar to an asteroid but lacks the technical criteria to be classified as such. PlutoSDR is an active learning module, similar to software-defined radio, but it also lacks the corresponding performance or technical criteria to be classified as such in the official view.
PlutoSDR can serve as a key to open the door to communication or SDR courses, but it cannot replace existing more professional SDRs. PlutoSDR is designed for students and is also more affordable. Therefore, all users of PlutoSDR should be aware of its limitations in many aspects to ensure normal operation and use.
The radio chip AD9363 within ADALM-PLUTO is a high-performance, highly integrated RF agile transceiver based on a direct conversion receiver. * The receiving subsystem includes a low-noise amplifier (LNA), direct conversion mixer, configurable analog filter, high-speed analog-to-digital converter (ADC), digital decimation filter, and 128-tap finite impulse response (FIR) filter, capable of producing 12-bit output signals at appropriate sampling rates. The receiving chain is amplified through configurable automatic gain control (AGC) or manual gain mode, DC bias correction, and quadrature correction. The received I and Q signals are passed to the digital baseband processor, in this case, the Xilinx Zynq SoC. * The transmission subsystem also uses a direct conversion structure. It receives 12-bit I/Q samples from the baseband processor (also the Xilinx Zynq SoC in this case) and outputs to the antenna through a 128-tap finite impulse response (FIR) filter, digital interpolation filter, high-speed digital-to-analog converter (DAC), analog filter, direct conversion mixer, and low-power amplifier (PA). * The integrated phase-locked loop (PLL) within AD9363 provides clock and local oscillator for the receiving and transmitting channels and provides clock and sampling frequency for the ADC and DAC.
The Xilinx Zynq all-programmable SoC (AP SoC) integrates ARM processor programmability and FPGA hardware programmability, featuring a single-core ARM Cortex™-A9 processor paired with 28nm Artix®-7 basic programmable logic. It comes equipped with common hardware peripherals (USB, SPI, etc.).
Transceiver Structure
The AD9363 transmission chain is based on direct conversion technology. Although this block diagram belongs to AD9361, it also applies to AD9363 in the ADDALM-PLUTO. The difference between the two lies in the adjustable range and the absence of secondary functions (DCXO, no external LO, RF channel bandwidth narrowing).
Some considerations are as follows: – The Tx LO amplitude remains unchanged, so to receive the best signal, the DAC should be operated at the maximum bit depth possible, and then the output attenuation should be adjusted to change the output signal strength (do not just reduce the DAC input). The maximum bit depth of the DAC is 12 bits, but in practice, using the HDL provided by ADI requires generating a 16-bit signal, where the lower 4 bits LSB will be discarded.
Related Parameters
USB2.0
USB2.0 is a 480 Mbit/s half-duplex serial protocol.
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At 100% utilization, 480 megabits per second equals 60 megabytes per second.
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The chairman of the USB developer forum pointed out, “Due to the communication protocol overhead between storage cards and peripherals, the claimed maximum speed of 60MB/s for high-speed USB is at least 10-15% below peak.” This results in a speed drop to about 50MB/s.
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USB has four types of transfer modes: control transfer, interrupt transfer, synchronous transfer, and bulk transfer. When we use bulk transfer, it is impossible to turn off other modes, and resources will have a 10% loss, thus reducing the speed to about 45MB/s.
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In half-duplex transmission, sending and receiving occupy about 22.5MB/s respectively.
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The length of a single sample is 2 bytes (12 bits), resulting in a sampling rate of 11MSPS.
In practice, the sampling rate in PlutoSDR is close to 7.5 – 12.5 MSPS, but it depends on the USB host and the current network conditions. The actual rate is approximately 65%-100% of the theoretical rate, indicating that while the rate primarily depends on the host, there is still room for optimization. Compared to existing commercial transmission rates of several Gbps Ethernet, USB 3.0 (5 Gbps full duplex), or PCIe (4 Gbps per channel), USB 2.0 is still much slower.
FPGA Specifications
The FPGA inside PlutoSDR (as part of the Xilinx Zynq 7010) is quite small
| Attribute | Size |
|---|---|
| Logic Units | 28 |
| Block Memory | 2.1 |
| DSP Slices | 80 |
The design goals for using part of the FPGA are: – CMOS interface implementation – I/Q conversion (if needed by the user) – DDS (for the transmission end’s multi-tone generator), and – Adding 8 interpolators/decimators to lower the sampling rate of PlutoSDR by 8 times compared to AD9363’s minimum sampling rate of 520.833kSPS (65.104166 kSPS)
The following utilization report is a relatively typical case. If you do not need some of the logic circuits mentioned above, you can turn them off and repurpose the FPGA as custom logic circuits.
Additional decimation and interpolation filters use 20 DSP slices (a total of 40). Optional DDS uses 20 DSP slices, and optional 2 x 2 matrix multiplication (sometimes used for IQ correction or phase rotation) is 2 per channel, with one DC filter per channel.
Using different Zynq devices can easily overcome this issue—we chose a device with the minimum pin count which helps to make the layout more reasonable at a lower price. Using larger devices and packages will affect size and cost.
PlutoSDR does not have an RF shielding module, which means placing a powerful transmitter (like your phone) nearby may affect the tuning results of PlutoSDR. This shortcoming can be overcome by adding RF shielding devices, but it will increase costs and size.
There are no pre-select or output filters on PlutoSDR, and the output from the AD9363 is from the SMA connector, while the input provided by the pins of AD9363 goes into the device’s antenna.
The RF transmitter output LO frequency in AD9363 has moderate third harmonics. If your LO is 3 GHz (where the third harmonic is 9 GHz, exceeding the balun range used for differential to single-ended conversion in PlutoSDR), this frequency will be quite low. However, if the LO is 500 MHz, the third harmonic will be 1500 MHz, well within range. If you transmit RF signals at 500 MHz, the signal will propagate at 1500 MHz.
Conclusion
AlthoughAD9363‘s RF performance is sufficient for many RF applications, it does not match the specifications of potentially other high-performance devices, such as AD9361, AD9364, or AD9371 found in other commercial SDR devices.
PlutoSDR performs better than many similar devices, but it is not the best SDR.
However, due to PlutoSDR’s ease of use and lower price, it remains one of the best choices for entry-level software-defined radio (SDR).
【References】
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https://wiki.seeedstudio.com/cn/ADALM-PLUTO-Overview/
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https://zhuanlan.zhihu.com/p/54190140
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https://www.analog.com/cn/design-center/evaluation-hardware-and-software/evaluation-boards-kits/ADALM-PLUTO.html
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https://wiki.analog.com/university/tools/pluto
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https://wiki.analog.com/university/tools/pluto/users
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https://wiki.analog.com/university/tools/pluto/developers
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https://wiki.analog.com/university/tools/pluto/hackers
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