How Microcontrollers Work: Detailed Structure and Principles

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The basic structure of a microcontroller includes six parts: Central Processing Unit (CPU), memory, timer/counter, input/output interface, interrupt control system, and clock circuit.

1. Basic Components

Central Processing Unit (CPU)

It consists of an arithmetic logic unit and a control unit, which are the core of the microcontroller. The arithmetic logic unit is used for various calculations, while the control unit coordinates the operation of different parts of the microcontroller.

Memory

Used to store programs and raw data.

Clock Circuit

The clock circuit generates control signals for the microcontroller to execute instructions in strict timing order.

Timer/Counter: Implements timing or counting functions.

The input/output interface (I/O) facilitates data transfer between the microcontroller and other devices.

Interrupt Control System: Responds to interrupt requests from interrupt sources.

2. Microcontroller Pins

Dual In-line Package (DIP)

Plastic Leaded Chip Carrier (PLCC)

Power Pins: VCC (pin 40) and VSS (pin 20) connect to the positive and negative terminals of the power supply, respectively.

Clock Circuit Pins: The microcontroller needs clock pulse signals to operate, connected via pins (18) and (19) to the oscillator circuit.

The control signal pins include the following four:

EA (pin 31): When EA is high, it first executes the internal ROM program, and when low, it only executes the external ROM program.

RST (pin 9): When a high signal lasting more than two machine cycles is input, it resets the microcontroller, initializing it to re-execute the program.

ALE (pin 30): Controls the time-sharing transfer of the lower 8 bits of address and data when accessing external memory and other peripherals.

PSEN (pin 29): External program memory read select signal.

There are 32 parallel input/output pins:

PO ports (pins 39-32): Can be used as address/data bus ports or as general I/O ports.

P1 ports (pins 1-8): Generally used only as I/O ports.

P2 ports (pins 21-28): Can output the upper 8 bits of address when accessing external memory, and can also be used as general I/O ports.

P3 ports (pins 10-17): Mainly used for their secondary functions, but can also be used as general I/O ports.

3. Parallel Input/Output

P0 port circuit structure

1 data output latch.

2 tri-state data input buffers BUF1 and BUF2.

2 field-effect transistors (FET).

1 multiplexer, 1 inverter, and 1 AND gate.

P0 Port Working Principle – Used as Multiplexed Address/Data Bus

Output: When the “control” signal is 1, the hardware automatically connects the switch MUX to the upper part, activating the output of the inverter, and enabling the “AND gate”.

① When the output address/data information = 1, the “AND gate” output is 1, the upper field-effect transistor conducts, and the lower field-effect transistor is off, resulting in P0.x pin outputting 1.

② When the output address/data information = 0, the upper field-effect transistor is off, the lower field-effect transistor conducts, leading to P0.x pin outputting 0.

P0 Port Working Principle – Used as Multiplexed Address/Data Bus

Input: When the P0 port is used as data input, it only reads information from the external pins, with the “control” signal being 0, and MUX connecting to the Q terminal of the latch.

When the P0 port accesses external memory in a multiplexed address/data manner, the CPU automatically writes FFH to the P0 port, turning off the lower field-effect transistor, while the upper field-effect transistor is also off due to the control signal being 0, ensuring high impedance input for data coming from the outside directly through the P0.x pin via the input buffer BUF2 into the internal bus.

① When the D latch is 1, the terminal is 0, the lower field-effect transistor is off, and the output is open-drain; thus, an external pull-up resistor is needed to output a high level;

② When the D latch is 0, the lower field-effect transistor conducts, and the P0 port outputs a low level.

P0 Port Working Principle – Used as General I/O Port

Input: Two reading methods: “Read Latch” and “Read Pin”.

① When the CPU issues a “Read Latch” instruction, the status of the latch is transferred from the Q terminal through the upper tri-state buffer BUF1 into the internal bus.

② When the CPU issues a “Read Pin” instruction, the output state of the latch Q=1 (Q terminal is 0), turning off the lower field-effect transistor, and the state of the pin is transferred through the lower tri-state buffer BUF2 into the internal bus.

P1 port circuit structure

1 data output latch.

2 tri-state data input buffers BUF1 and BUF2.

1 field-effect transistor (FET) and 1 internal pull-up resistor.

P1 Port Working Principle – Used Only as General I/O Port

① If the CPU outputs 1, Q=1, Q-=0, the field-effect transistor is off, and P1.x pin outputs 1;

② If the CPU outputs 0, Q=0, Q-=1, the field-effect transistor conducts, and P1.x pin outputs 0.

P1 Port Working Principle – Used Only as General I/O Port

Input: Divided into “Read Latch” and “Read Pin”

① Read “Latch”, the output Q state enters the internal bus via the input buffer BUF1;

② “Read Pin”, first write 1 to the latch, turning off the field-effect transistor, and the level at the P1.x pin enters the internal bus via the input buffer BUF2.

P2 port circuit structure

1 data output latch.

2 tri-state data input buffers BUF1 and BUF2.

1 field-effect transistor (FET) and 1 internal pull-up resistor.

1 multiplexer MUX

P2 Port Working Principle – Used as Address Bus

Under the control signal, the MUX connects to the “address”.

① When the “address” is 0, the field-effect transistor conducts, and the P2 port pin outputs 0;

② When the “address” line is 1, the field-effect transistor is off, and the P2 port pin outputs 1.

P2 Port Working Principle – Used as General I/O Port

Output: Under the influence of internal control signals, the MUX connects to the Q terminal of the latch.

① When the CPU outputs 1, Q=1, the field-effect transistor is off, and P2.x pin outputs 1;

② When the CPU outputs 0, Q=0, the field-effect transistor conducts, and P2.x pin outputs 0.

P2 Port Working Principle – Used as General I/O Port

Input: Divided into “Read Latch” and “Read Pin” methods.

① When “Read Latch”, the Q terminal signal enters the internal bus via the input buffer BUF1;

② When “Read Pin”, first write 1 to the latch, turning off the field-effect transistor, and the level at the P2.x pin enters the internal bus via the input buffer BUF2.

P3 Port Circuit Structure

1 data output latch.

3 tri-state data input buffers BUF1 and BUF2.

1 field-effect transistor (FET) and 1 internal pull-up resistor.

1 multiplexer MUX and 1 NAND gate.

P3 Port Working Principle – Used for Secondary Function

Output: The latch for this bit needs to be set to “1” to enable the NAND gate.

When the second output is 1, the field-effect transistor is off, and P3.x pin outputs 1;

When the second output is 0, the field-effect transistor conducts, and P3.x pin outputs 0.

P3 Port Working Principle – Used for Secondary Function

Input: The latch for this bit and the second output function terminal must both be set to 1 to ensure the field-effect transistor is off, and the information at P3.x pin is obtained from the output of the input buffer BUF3.

P3 Port Working Principle – Used as General I/O Port

Output: The second output function terminal should remain “1”, allowing the NAND gate to be enabled.

When the CPU outputs 1, Q=1, the field-effect transistor is off, and P3.x pin outputs 1;

When the CPU outputs 0, Q=0, the field-effect transistor conducts, and P3.x pin outputs 0.

P3 Port Working Principle – Used as General I/O Port

Input: The output latch at P3.x and the second output function must both be set to 1 for the field-effect transistor to be off.

The information at P3.x pin is transferred through input buffers BUF3 and BUF2 into the internal bus, completing the “Read Pin” operation;

It can also perform the “Read Latch” operation, where the Q terminal information is transferred through buffer BUF1 into the internal bus.

All four parallel ports (P0-P3) need to set the latch to “1” before reading pins, ensuring the field-effect transistors are off to avoid interference with data in the latch.

Since an additional action of setting “1” is required before input operations, they are referred to as “quasi-bidirectional ports”.

All four parallel ports (P0-P3) are quasi-bidirectional ports.

4. Minimum System Board of 8051 Microcontroller

The 8051 microcontroller has 4KB of flash memory, making it a minimal application system for digital input/output.

When constructing the minimum application system for the 8051 microcontroller, it only needs to connect an external clock circuit and reset circuit, as shown below.

Note: This minimum application system can only serve as a small digital measurement and control unit.

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1. Basic Components

2. Microcontroller Pins

3. Parallel Input/Output

4. Minimum System Board of 8051 Microcontroller

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