Comprehensive Guide to ESP32-S3 Pin References

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GPIO Pins Not Recommended for Use

Used for communication with the flash/PSRAM inside the package, not recommended for other purposes.

Pin	Function
GPIO 26	SPICS1
GPIO 27	SPIHD
GPIO 28	SPIWP
GPIO 29	SPICS0
GPIO 30	SPICLK
GPIO 31	SPIQ
GPIO 32	SPID

Restricted GPIO Pins

Generally have important functions, adjust usage as needed.

Pin	Function
GPIO 0	Chip boot mode
GPIO 3	JTAG signal source
GPIO 19	UART interface – usually used for debugging.
GPIO 20	UART interface – usually used for debugging.
GPIO 45	VDD_SPI voltage
GPIO 46	Chip boot mode/ROM code log printing

ADC2 – unrestricted, unless Wi-Fi is constantly connected. ADC2_CH(n) analog functions cannot be used simultaneously with Wi-Fi.

No DAC in ESP32-S3

There is no DAC function in ESP32-S3, this needs to be noted.

ESP32-S3 Peripheral Devices

45x GPIOs

The following list is an overview of all pins in ESP32-S3, which includes 45 GPIO pins:

Pin	Pin	Pin	Power Pins 3-6	Pin Configuration 7	Pin Function 1,2
Index	Name	Type 1	Reset	Post Reset	IO MUX	RTC	Analog
1	LNA_IN	Analog
2	VDD3P3	Power
3	VDD3P3	Power
4	CHIP_PU	Analog	VDD3P3_RTC
5	GPIO0	IO	VDD3P3_RTC	IE, WPU	IE, WPU	IO MUX	RTC
6	GPIO1	IO	VDD3P3_RTC	IE	IE	IO MUX	RTC	Analog
7	GPIO2	IO	VDD3P3_RTC	IE	IE	IO MUX	RTC	Analog
8	GPIO3	IO	VDD3P3_RTC	IE	IE	IO MUX	RTC	Analog
9	GPIO4	IO	VDD3P3_RTC	IO MUX	RTC	Analog
10	GPIO5	IO	VDD3P3_RTC	IO MUX	RTC	Analog
11	GPIO6	IO	VDD3P3_RTC	IO MUX	RTC	Analog
12	GPIO7	IO	VDD3P3_RTC	IO MUX	RTC	Analog
13	GPIO8	IO	VDD3P3_RTC	IO MUX	RTC	Analog
14	GPIO9	IO	VDD3P3_RTC	IE	IO MUX	RTC	Analog
15	GPIO10	IO	VDD3P3_RTC	IE	IO MUX	RTC	Analog
16	GPIO11	IO	VDD3P3_RTC	IE	IO MUX	RTC	Analog
17	GPIO12	IO	VDD3P3_RTC	IE	IO MUX	RTC	Analog
18	GPIO13	IO	VDD3P3_RTC	IE	IO MUX	RTC	Analog
19	GPIO14	IO	VDD3P3_RTC	IE	IO MUX	RTC	Analog
20	VDD3P3_RTC	Power
21	XTAL_32K_P	IO	VDD3P3_RTC	IO MUX	RTC	Analog
22	XTAL_32K_N	IO	VDD3P3_RTC	IO MUX	RTC	Analog
23	GPIO17	IO	VDD3P3_RTC	IE	IO MUX	RTC	Analog
24	GPIO18	IO	VDD3P3_RTC	IE	IO MUX	RTC	Analog
25	GPIO19	IO	VDD3P3_RTC	IO MUX	RTC	Analog
26	GPIO20	IO	VDD3P3_RTC	IO MUX	RTC	Analog
27	GPIO21	IO	VDD3P3_RTC	IO MUX	RTC
28	SPICS1	IO	VDD_SPI	IE, WPU	IE, WPU	IO MUX
29	VDD_SPI	Power
30	SPIHD	IO	VDD_SPI	IE, WPU	IE, WPU	IO MUX
31	SPIWP	IO	VDD_SPI	IE, WPU	IE, WPU	IO MUX
32	SPICS0	IO	VDD_SPI	IE, WPU	IE, WPU	IO MUX
33	SPICLK	IO	VDD_SPI	IE, WPU	IE, WPU	IO MUX
34	SPIQ	IO	VDD_SPI	IE, WPU	IE, WPU	IO MUX
35	SPID	IO	VDD_SPI	IE, WPU	IE, WPU	IO MUX
36	SPICLK_N	IO	VDD_SPI / VDD3P3_CPU	IE	IE	IO MUX
37	SPICLK_P	IO	VDD_SPI / VDD3P3_CPU	IE	IE	IO MUX
38	GPIO33	IO	VDD_SPI / VDD3P3_CPU	IE	IO MUX
39	GPIO34	IO	VDD_SPI / VDD3P3_CPU	IE	IO MUX
40	GPIO35	IO	VDD_SPI / VDD3P3_CPU	IE	IO MUX
41	GPIO36	IO	VDD_SPI / VDD3P3_CPU	IE	IO MUX
42	GPIO37	IO	VDD_SPI / VDD3P3_CPU	IE	IO MUX
43	GPIO38	IO	VDD3P3_CPU	IE	IO MUX
44	MTCK	IO	VDD3P3_CPU	IE 8	IO MUX
45	MTDO	IO	VDD3P3_CPU	IE	IO MUX
46	VDD3P3_CPU	Power
47	MTDI	IO	VDD3P3_CPU	IE	IO MUX
48	MTMS	IO	VDD3P3_CPU	IE	IO MUX
49	U0TXD	IO	VDD3P3_CPU	IE, WPU	IE, WPU	IO MUX
50	U0RXD	IO	VDD3P3_CPU	IE, WPU	IE, WPU	IO MUX
51	GPIO45	IO	VDD3P3_CPU	IE, WPD	IE, WPD	IO MUX
52	GPIO46	IO	VDD3P3_CPU	IE, WPD	IE, WPD	IO MUX
53	XTAL_N	Analog
54	XTAL_P	Analog
55	VDDA	Power
56	VDDA	Power
57	GND	Power

4x SPI

ESP32-S3 has the following SPI interfaces:

• SPI0, for ESP32-S3 and encrypted DMA (EDMA) access to internal or external flash/PSRAM

• SPI1, for CPU access to internal or external flash/PSRAM

• SPI2, general SPI controller with a separate DMA channel

• SPI3, general SPI controller, shares a DMA channel with some peripherals

SPI0 and SPI1 features

• Supports single, dual, quad, and octal SPI modes

• Octal SPI mode supports Single Data Rate (SDR) and Double Data Rate (DDR)

• Clock frequency configurable, up to 120 MHz in octal SPI SDR/DDR mode

• Data transfer in byte units

SPI2 features

• Supports host or slave mode

• Has a separate DMA channel

• Supports single, dual, quad, and octal SPI modes

• Clock polarity (CPOL) and phase (CPHA) configurable

• Clock frequency configurable • Data transfer in byte units

• Read and write data bit order configurable: Most Significant Bit (MSB) first, or Least Significant Bit (LSB) first

• Host mode

• Supports dual-line full-duplex communication, clock frequency up to 80 MHz

• Octal SPI full-duplex mode only supports single data rate (SDR)

• Supports single, dual, quad, and octal half-duplex communication, clock frequency up to 80 MHz

• Octal SPI half-duplex mode supports single data rate (up to 80 MHz) and double data rate (up to 40 MHz)

• Supports Moto6800/I8080/parallel RGB interface 8-bit LCD driving

• Has six SPI_CS pins that can connect to six independent SPI slaves

• CS setup and hold time configurable

• Slave mode

• Supports dual-line full-duplex communication, clock frequency up to 60 MHz

• Supports single, dual, and quad half-duplex communication, clock frequency up to 60 MHz

• Octal SPI full-duplex and half-duplex modes only support single data rate (SDR)

SPI3 features

• Supports host or slave mode

• Shares a DMA channel with ADC and DAC peripherals

• Supports single, dual, quad, and octal SPI modes

• Octal SPI mode only supports single data rate (SDR)

• Clock polarity (CPOL) and phase (CPHA) configurable

• Clock frequency configurable • Data transfer in byte units

• Read and write data bit order configurable: Most Significant Bit (MSB) first, or Least Significant Bit (LSB) first

• Host mode

• Supports dual-line full-duplex communication, clock frequency up to 80 MHz

• Supports single, dual, and quad half-duplex communication, clock frequency up to 80 MHz

• Supports 1-bit LCD driving

• Has three SPI_CS pins that can connect to three independent SPI slaves

• CS setup and hold time configurable

• Slave mode – supports dual-line full-duplex communication, clock frequency up to 60 MHz

• Supports single, dual, and quad half-duplex communication, clock frequency up to 60 MHz

Interface	Recommended IO MUX Pins	Connected via GPIO Swap Matrix
SPI0/1	See Table 2-3 IO MUX and GPIO Pin Function Description 5c, 5d –	–
SPI2	See Table 2-3 IO MUX and GPIO Pin Function Description 5e	Any IO pin
SPI3	Any IO pin

3x UART

ESP32-S3 has three UART (Universal Asynchronous Receiver-Transmitter) controllers, namely UART0, UART1, UART2, supporting asynchronous communication (RS232 and RS485) and IrDA, with a communication rate of up to 5 Mbps. The UART controllers have the following features:

• Supports three configurable clock sources

• Programmable baud rate for transmission

• Three UART’s transmit FIFO and receive FIFO share 1024 x 8-bit RAM

• Full-duplex asynchronous communication

• Supports input signal baud rate self-check function

• Supports 5/6/7/8 bit data length

• Supports 1/1.5/2/3 stop bits

• Supports parity bit

• Supports AT_CMD special character detection

• Supports RS485 protocol

• Supports IrDA protocol

• Supports GDMA high-speed data communication

• Supports UART wake-up mode

• Supports software flow control and hardware flow control

Each UART is assigned default GPIOs, but these pins may conflict with embedded flash, onboard PSRAM, or peripherals based on your ESP32 circuit design.

Any GPIO can be used for hardware UART using the GPIO matrix, so to avoid conflicts, simply provide tx and rx pins at construction.

Below are the default pins for ESP32-S3 UART.

UART0	UART1	UART2
Transmit (TX)	IO43	IO17 / Any IO	Any IO
Receive (RX)	IO44	IO18 / Any IO	Any IO

2x I2C

ESP32-S3 has two I2C bus interfaces, which can be configured as I2C master or slave mode depending on user configuration. The I2C interface supports:

• Standard mode (100 Kbit/s)

• Fast mode (400 Kbit/s)

• Speed up to 800 Kbit/s, but limited by SCL and SDA pull-up strength

• 7-bit addressing mode and 10-bit addressing mode

• Dual-address (slave address and slave register address) addressing mode

Users can control the I2C interface more conveniently through the instruction abstraction layer provided by the I2C hardware.

For detailed information, please refer to the “ESP32-S3 Technical Reference Manual” > Chapter I2C Controller.

The I2C bus divides software and hardware objects, hardware can define 0 and 1, and I2C functionality can be implemented on any pin through configuration. Below is the default pin table for I2S:

I2C(0)	I2C(1)
SCL	IO0	IO2
SDA	IO1	IO3

14x Touch

ESP32-S3 provides up to 14 capacitive sensing GPIOs, capable of detecting capacitance changes caused by direct touch or proximity of fingers or other objects. This design features low noise and high sensitivity, suitable for supporting relatively small touch panels. Touch panel arrays can also be used in designs to detect larger areas or more points. The touch sensor of ESP32-S3 also supports waterproofing and digital filtering functions to further enhance sensor performance.

Note: The ESP32-S3 touch sensor is currently unable to pass the RF immunity test system (CS) certification, limiting application scenarios.

Pin	RTC / Analog	RTC Function	Analog Function
Index	IO Name	0	1	2	3	0	1
5	RTC_GPIO0	RTC_GPIO0	sar_i2c_scl_0
6	RTC_GPIO1	RTC_GPIO1	sar_i2c_sda_0	TOUCH1	ADC1_CH0
7	RTC_GPIO2	RTC_GPIO2	sar_i2c_scl_1	TOUCH2	ADC1_CH1
8	RTC_GPIO3	RTC_GPIO3	sar_i2c_sda_1	TOUCH3	ADC1_CH2
9	RTC_GPIO4	RTC_GPIO4	TOUCH4	ADC1_CH3
10	RTC_GPIO5	RTC_GPIO5	TOUCH5	ADC1_CH4
11	RTC_GPIO6	RTC_GPIO6	TOUCH6	ADC1_CH5
12	RTC_GPIO7	RTC_GPIO7	TOUCH7	ADC1_CH6
13	RTC_GPIO8	RTC_GPIO8	TOUCH8	ADC1_CH7
14	RTC_GPIO9	RTC_GPIO9	TOUCH9	ADC1_CH8
15	RTC_GPIO10	RTC_GPIO10	TOUCH10	ADC1_CH9
16	RTC_GPIO11	RTC_GPIO11	TOUCH11	ADC2_CH0
17	RTC_GPIO12	RTC_GPIO12	TOUCH12	ADC2_CH1
18	RTC_GPIO13	RTC_GPIO13	TOUCH13	ADC2_CH2
19	RTC_GPIO14	RTC_GPIO14	TOUCH14	ADC2_CH3
21	RTC_GPIO15	RTC_GPIO15	XTAL_32K_P	ADC2_CH4
22	RTC_GPIO16	RTC_GPIO16	XTAL_32K_N	ADC2_CH5
23	RTC_GPIO17	RTC_GPIO17	ADC2_CH6
24	RTC_GPIO18	RTC_GPIO18	ADC2_CH7
25	RTC_GPIO19	RTC_GPIO19	USB_D-	ADC2_CH8
26	RTC_GPIO20	RTC_GPIO20	USB_D+	ADC2_CH9
27	RTC_GPIO21	RTC_GPIO21

2x I2S

ESP32-S3 has two standard I2S interfaces that can operate in master or slave mode, in full duplex or half duplex, and can be configured for I2S serial 8/16/24/32 bit data transmission mode, supporting BCK clock frequencies from 10 kHz to 40 MHz. The I2S interface has dedicated DMA controllers. Supports TDM PCM, TDM MSB aligned, TDM LSB aligned, TDM Phillips, PDM interface.

Any IO pin can be configured for I2S

RMT

Infrared remote control (RMT) supports transmitting and receiving infrared control signals, with the following features:

• Four channels support transmission

• Four channels support reception

• Programmable configuration for multiple channels to transmit simultaneously

• Eight channels of RMT share 384 x 32-bit RAM

• Transmitting pulses support carrier modulation

• Receiving pulses support filtering and carrier demodulation

• Ping-pong transmission mode

• Ping-pong reception mode

• Transmitter supports continuous transmission

• Transmission channel 3 supports DMA access

• Reception channel 7 supports DMA access

RMT Application Reference

ESP32-C3 Getting Started Tutorial Basic Edition (Five, RMT Application – Control SK6812 Full Color RGB Light)

LED PWM

LED PWM controller can be used to generate eight independent digital waveforms, with the following features:

• Configurable waveform period and duty cycle, with a signal period of 1 ms, duty cycle accuracy up to 14 bits

• Multiple clock source options, including: APB bus clock, external main oscillator clock

• Can operate in Light-sleep mode

• Supports hardware automatic stepwise increase or decrease of duty cycle, can be used for LED RGB color gradient generator

For detailed information, please refer to the “ESP32-S3 Technical Reference Manual” > Chapter LED PWM Controller.

Any GPIO pin can be configured for LED PWM, up to eight independent channels can be configured.

USB-OTG

ESP32-S3 features an integrated USB On-The-Go (hereafter referred to as OTG_FS) peripheral with a transceiver. This OTG_FS peripheral can be configured as Host mode or Device mode, fully compliant with USB 2.0 protocol specifications. It supports full-speed mode (12 Mbit/s) and low-speed mode (1.5 Mbit/s), and also supports Host Negotiation Protocol (HNP) and Session Request Protocol (SRP).

TWAI

Two-wire automotive interface (TWAI®) protocol is a multi-master, multicast communication protocol with error detection, transmission error signaling, and built-in message priority arbitration functions. The TWAI protocol is suitable for automotive and industrial applications (see Chapter 31.3). ESP32-S3 contains a TWAI controller that can connect to the TWAI bus via an external transceiver. The TWAI controller includes a series of advanced functions, widely applicable for automotive products, industrial automation control, building automation, etc.

2x 12-bit ADC

ESP32-S3 integrates two 12-bit SAR ADCs, supporting a total of 20 analog channel inputs. To achieve lower power consumption, the ULP coprocessor of ESP32-S3 can also measure voltage in sleep mode, and the CPU can be awakened by setting thresholds or other triggering methods.

1x LCD_CAMERA

ESP32-S3’s LCD_CAM controller contains independent LCD and Camera modules. The LCD module is used to send parallel video data signals, supporting interfaces such as RGB, MOTO6800, and I8080 timing. The Camera module is used to receive parallel video data signals, supporting DVP 8-/16-bit mode.

ESP32-S3 supports 8-bit to 16-bit parallel RGB, I8080, MOTO6800 interfaces, supporting clock frequencies less than 40 MHz. Supports conversion between RGB565, YUV422, YUV420, and YUV411.

The camera interface of ESP32-S3 supports 8-bit to 16-bit DVP image sensor interface, supporting clock frequencies less than 40 MHz. Supports conversion between RGB565, YUV422, YUV420, and YUV411.

SD/MMC Host Controller

ESP32-S3 integrates an SD/MMC host controller, supporting the following features: • SD card versions 3.0 and 3.01 • SDIO version 3.0 • CE-ATA version 1.1 • Multimedia card (MMC versions 4.41, eMMC 4.5, and 4.51) • Clock output up to 80 MHz • Three data bus modes: – 1-bit – 4-bit (supports two SD/SDIO/MMC 4.41 cards, and one SD card working at 1.8 V voltage) – 8-bit For detailed information, please refer to the “ESP32-S3 Technical Reference Manual” > Chapter SD/MMC Host Controller.

MCPWM

Motor control pulse width modulator (MCPWM) ESP32-S3 contains two MCPWM units that can be used to drive digital motors and smart lights. Each MCPWM peripheral includes a clock prescaler (pre-divider), three PWM timers, three PWM operators, and a capture module. The PWM timers are used to generate timing references. The PWM operators generate the desired waveform based on the timing reference. By configuration, any PWM operator can use the timing reference from any PWM timer. Different PWM operators can use the timing reference from the same PWM timer to produce PWM signals. Additionally, different PWM operators can use different values from different PWM timers to generate separate PWM signals. Different PWM timers can also be synchronized. For detailed information, please refer to the “ESP32-S3 Technical Reference Manual” > Chapter Motor Control Pulse Width Modulator.

Summary Table of Peripheral and Sensor Pin Assignments

Interface	Signal	Pin	Function
ADC	ADC1_CH0	GPIO1	Two 12-bit SAR ADCs
ADC1_CH1	GPIO2
ADC1_CH2	GPIO3
ADC1_CH3	GPIO4
ADC1_CH4	GPIO5
ADC1_CH5	GPIO6
ADC1_CH6	GPIO7
ADC1_CH7	GPIO8
ADC1_CH8	GPIO9
ADC1_CH9	GPIO10
ADC2_CH0	GPIO11
ADC2_CH1	GPIO12
ADC2_CH2	GPIO13
ADC2_CH3	GPIO14
ADC2_CH4	XTAL_32K_P
ADC2_CH5	XTAL_32K_N
ADC2_CH6	GPIO17
ADC2_CH7	GPIO18
ADC2_CH8	GPIO19
ADC2_CH9	GPIO20
Interface	Signal	Pin	Function
Touch Sensor	TOUCH1	GPIO1	Capacitive touch sensor
TOUCH2	GPIO2
TOUCH3	GPIO3
TOUCH4	GPIO4
TOUCH5	GPIO5
TOUCH6	GPIO6
TOUCH7	GPIO7
TOUCH8	GPIO8
TOUCH9	GPIO9
TOUCH10	GPIO10
TOUCH11	GPIO11
TOUCH12	GPIO12
TOUCH13	GPIO13
TOUCH14	GPIO14
JTAG	MTDI	MTDI	Software debugging JTAG
MTCK	MTCK
MTMS	MTMS
MTDO	MTDO
UART	U0RXD_in	Any GPIO pin	Three UART devices, supporting hardware flow control and DMA
U0CTS_in
U0DSR_in
U0TXD_out
U0RTS_out
U0DTR_out
U1RXD_in
U1CTS_in
U1DSR_in
U1TXD_out
U1RTS_out
U1DTR_out
U2RXD_in
U2CTS_in
U2DSR_in
U2TXD_out
U2RTS_out
U2DTR_out
I2C	I2CEXT0_SCL_in/_out	Any GPIO pin	Two I2C devices, supporting master or slave mode
I2CEXT0_SDA_in/_out
I2CEXT1_SCL_in/_out
I2CEXT1_SDA_in/_out
LED PWM	LEDC_LS_SIG_out0~7	Any GPIO pin	Eight independent channels
Interface	Signal	Pin	Function
I2S	I2S0O_BCK_in	Any GPIO pin	For serial stereo data input and output.
I2S0_MCLK_in
I2S0O_WS_in
I2S0I_SD_in
I2S0I_SD1_in
I2S0I_SD2_in
I2S0I_SD3_in
I2S0I_BCK_in
I2S0I_WS_in
I2S1O_BCK_in
I2S1_MCLK_in
I2S1O_WS_in
I2S1I_SD_in
I2S1I_BCK_in
I2S1I_WS_in
I2S0O_BCK_out
I2S0_MCLK_out
I2S0O_WS_out
I2S0O_SD_out
I2S0O_SD1_out
I2S0I_BCK_out
I2S0I_WS_out
I2S1O_BCK_out
I2S1_MCLK_out
I2S1O_WS_out
I2S1O_SD_out
I2S1I_BCK_out
I2S1I_WS_out
LCD_CAMERA	LCD_PCLK	Any GPIO pin	For sending 8 ~16 bit LCD
LCD_DC	Sending and receiving interface data for 8 ~16
LCD_V_SYNC	Receiving camera interface data.
LCD_H_SYNC
LCD_H_ENABLE
LCD_DATA_out0~15
LCD_CS
CAM_CLK
CAM_V_SYNC
CAM_H_SYNC
CAM_H_ENABLE
CAM_PCLK
CAM_DATA_in0~15
IR Remote Control	RMT_SIG_in0~3	Any GPIO pin	Four-way IR transceiver, supporting different
RMT_SIG_out0~3	Waveform standards.
Interface	Signal	Pin	Function
SPI0/1	SPICLK_out_mux	SPICLK	Supports SPI, Dual SPI, Quad SPI, Octal SPI, QPI, and OPI, can connect to external flash and RAM.
SPICS0_out	SPICS0
SPICS1_out	SPICS1
SPID_in/_out	SPID
SPIQ_in/_out	SPIQ
SPIWP_in/_out	SPIWP
SPIHD_in/_out	SPIHD
SPID4_in/_out	GPIO33
SPID5_in/_out	GPIO34
SPID6_in/_out	GPIO35
SPID7_in/_out	GPIO36
SPIDQS_in/_out	GPIO37
SPI2	FSPICLK_in/_out_mux	Any GPIO pin	Supports the following functions:
FSPICS0_in/_out	•SPI, Dual SPI, Quad SPI, Octal SPI, QPI, and OPI in master mode, SPI, Dual SPI, Quad SPI, and QPI in slave mode;
FSPICS1~5_out	•Can connect to external flash, RAM, and other SPI devices
FSPID_in/_out	•Four clock modes for SPI transmission;
FSPIQ_in/_out	•Configurable SPI frequency;
FSPIWP_in/_out	•64-byte cache or DMA
FSPIHD_in/_out	Data cache.
FSPIIO4~7_in/_out
FSPIDQS_out
SPI3	SPI3_CLK_in/_out_mux	Any GPIO pin	Supports the following functions:
SPI3_CS0_in/_out	•Master and slave modes for SPI, Dual SPI, Quad SPI;
SPI3_CS1_out	•Four clock modes for SPI transmission;
SPI3_CS2_out	•Configurable SPI frequency;
SPI3_D_in/_out	•64-byte cache or DMA
SPI3_Q_in/_out	Data cache.
SPI3_WP_in/_out
SPI3_HD_in/_out
Pulse Counter	PCNT_SIG_CH0_in0~3	Any GPIO pin	Pulse counter captures pulses through seven modes and counts pulse edges.
PCNT_SIG_CH1_in0~3
PCNT_CTRL_CH0_in0~3
PCNT_CTRL_CH1_in0~3
Interface	Signal	Pin	Function
USB OTG	D-	GPIO19 (internal PHY use)	Full-speed USB OTG (USB
D+	GPIO20 (internal PHY use)	OTG supports using the chip’s internal integrated full-speed PHY, and also supports using external full-speed PHY)
VP	MTMS (external PHY use)
VM	MTDI (external PHY use)
RCV	GPIO21 (external PHY use)
OEN	MTDO (external PHY use)
VPO	MTCK (external PHY use)
VMO	GPIO38 (external PHY use)
USB Serial/JTAG Controller	D-	GPIO19 (internal PHY use)	Programming flash and CPU debugging
D+	GPIO20 (internal PHY use)	(USB Serial/JTAG controller supports using the chip’s internal integrated full-speed PHY, and also supports using external full-speed PHY)
VP	MTMS (external PHY use)
VM	MTDI (external PHY use)
OEN	MTDO (external PHY use)
VPO	MTCK (external PHY use)
VMO	GPIO38 (external PHY use)
SD/MMC	SDHOST_CCLK_out_1~2	Any GPIO pin	Supports V3.0.1 standard SD memory card
SDHOST_RST_N_1~2
SDHOST_CCMD_OD_PULLUP_EN_N
SDIO_TOHOST_INT_out
SDHOST_CCMD_in/_out_1
SDHOST_CCMD_in/_out_2
SDHOST_CDATA_in/_out_10
SDHOST_CDATA_in/_out_11
SDHOST_CDATA_in/_out_12
SDHOST_CDATA_in/_out_13
SDHOST_CDATA_in/_out_14
SDHOST_CDATA_in/_out_15
SDHOST_CDATA_in/_out_16
SDHOST_CDATA_in/_out_17
SDHOST_CDATA_in/_out_20
SDHOST_CDATA_in/_out_21
SDHOST_CDATA_in/_out_22
SDHOST_CDATA_in/_out_23
SDHOST_CDATA_in/_out_24
SDHOST_CDATA_in/_out_25
SDHOST_CDATA_in/_out_26
SDHOST_CDATA_in/_out_27
SDHOST_DATA_STROBE_1~2
SDHOST_CARD_DETECT_N_1~2
SDHOST_CARD_WRITE_PRT_1~2
SDHOST_CARD_INT_N_1~2
Interface	Signal	Pin	Function
MCPWM	PWM0_SYNC0~2_in	Any GPIO pin	Two MCPWM input/output pins, including differential output of PWM waveform, fault input signals to be detected, captured input signals, and external synchronization signals of PWM timers
PWM0_F0~2_in
PWM0_CAP0~2_in
PWM1_SYNC0~2_in
PWM1_F0~2_in
PWM1_CAP0~2_in
PWM0_out0a
PWM0_out0b
PWM0_out1a
PWM0_out1b
PWM0_out2a
PWM0_out2b
PWM1_out0a
PWM1_out0b
PWM1_out1a
PWM1_out1b
PWM1_out2a
PWM1_out2b
TWAI® Controller	TWAI_RX	Any GPIO pin	Compatible with ISO 11898-1 protocol
TWAI_TX	Any GPIO pin	Supports a maximum rate of 1 Mbit/s
TWAI_BUS_OFF_ON
TWAI_CLKOUT

References

ESP32-S3-DevKitC-1 Documentation: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/hw-reference/esp32s3/user-guide-devkitc-1.html

ESP32 S3 Pin Reference: https://github.com/bdring/FluidNC/wiki/ESP32-S3-Pin-Reference

ESP32-S3 Quick Reference Manual: https://docs.01studio.cc/esp32-s3/quickref.html

ESP32-S3 Series Chip Technical Specification: https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_cn.pdf

ESP32-S3-WROOM-1 ESP32-S3-WROOM-1U Technical Specification: https://www.espressif.com/sites/default/files/documentation/esp32-s3-wroom-1_wroom-1u_datasheet_cn.pdf