SiFive 2018 Tech Seminar
On May 17, the SiFive 2018 Tech Seminar, hosted by RISC-V and open-source hardware leader SiFive, and co-organized by CanSemi Semiconductor and China Integrated Circuit magazine, will be grandly held at the Changrong Crown Hotel in Shanghai.
With the rapid development of the RISC-V ecosystem, SiFive, a company founded by the inventors of the open-source RISC-V instruction set architecture, has launched silicon-validated RISC-V Core IP, becoming the actual leader of RISC-V cores, demonstrating higher efficiency than other instruction set architectures. Its cores have been applied in products from companies like Western Digital and Microsemi. At the same time, SiFive has launched the RISC-V-based Freedom SoC platform, greatly lowering the threshold for developing customized prototype chips, reinterpreting the chip customization industry, and empowering innovation in systems and applications.
As the first customized semiconductor company based on the free and open-source RISC-V instruction set architecture, SiFive will share at this seminar in Shanghai:
①:The history, current status, and future trends of RISC-V
②:A detailed introduction to the RISC-V ecosystem
③:The latest RISC-V cores and platforms, as well as rapid customization of prototype chips
④:SiFive‘s partners showcase the charm of RISC-V from the application perspective
Important Notice:
①:Due tothe professional nature of the conference, to ensure a good quality of the meeting and participant experience, this meetingis limited to participants at the “manager” level and above (including “managers”);
②:Theend of the document includesthe meeting agenda andregistration link
How Powerful is RISC-V?
RISC-V may seem a bit unfamiliar to you, but you are definitely familiar with instruction sets (ISA).
In the early days, most microprocessors were based on Complex Instruction Set Computing (CISC), but processor speeds were unsatisfactory. To improve processor speed, Reduced Instruction Set Computing (RISC) was born.
RISC-V = RISC (Reduced Instruction Set) + V (Variation and Vector). It includes a very small basic instruction set and a series of optional extended instruction sets. The most basic instruction set contains only 40 instructions, and through extensions, it also supports 64-bit and 128-bit operations as well as variable-length instructions. Other completed extensions include multiplication and division operations, atomic operations, floating-point operations, etc., while instruction sets under development include compressed instructions, bit operations, transactional storage, vector calculations, etc. The development of the instruction set also follows the open-source software development model, which is jointly accomplished by core developers and the open-source community.
This means! Through this series of instruction set extensions, you can almost build microprocessors suitable forany field, such as cloud computing, storage, parallel computing, virtualization/containerization, MCU, application processors, DSP processors, and more.
“For engineers, trying to get information from ordinary IP vendors is futile,” said Yunsup Lee, CTO and co-founder of SiFive. “Endless confidentiality agreements, evasive answers, and inescapable sales meetings just to get some basic evaluation materials make it feel like they don’t want to do business with you at all. Compared to the products provided by SaaS companies, the backwardness of this industry is simply unbelievable. When we founded SiFive, we wanted to change this situation. By adopting a ‘research-evaluate-purchase’ model, we made obtaining access to Coreplex IP licenses as easy as purchasing any software service.”
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