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FPGA is a programmable chip, thus the design methods for FPGA include both hardware and software design. Hardware includes FPGA chip circuits, memory, input/output interface circuits, and other devices, while software refers to the corresponding HDL programs and the now-popular embedded C programs.
Currently, microelectronic technology has developed to the SOC stage, which means Integrated System stage, representing a revolutionary change in design philosophy compared to Integrated Circuits (IC). SOC is a complex system that integrates the functions of a complete product onto a single chip, including core processors, storage units, hardware acceleration units, and numerous external device interfaces, characterized by long design cycles and high implementation costs. Therefore, its design method must be top-down, from system level to functional module, achieving seamless integration of software and hardware.
This enormous workload clearly exceeds the capabilities of a single engineer, thus requiring a hierarchical and structured design method for implementation. Initially, the chief designer divides the entire software development task into several operable modules, evaluates their interfaces and resources, drafts corresponding behavioral or structural models, and assigns them to the next level of designers. This allows multiple designers to simultaneously design different modules within a hardware system and be responsible for their assigned modules; then the upper-level designer verifies the functionality of the lower-level modules.
The top-down design process begins with system-level design, dividing it into several secondary units, and then further dividing each secondary unit into basic units until basic modules or IP cores can be directly implemented. Popular FPGA development tools provide hierarchical management, effectively organizing the intricate hierarchy and allowing easy access to the source code of a specific level module for error modification.
In engineering practice, there are also issues with software compilation time. Since large designs contain multiple complex functional modules, the timing convergence and simulation verification complexity are very high. To meet timing requirements, source files often need to be repeatedly modified, and the modified new versions need to be recompiled until the requirements are met. There are two issues here: first, software compilation can take hours or even weeks, which is intolerable for development; second, the results after recompilation and layout routing can vary greatly, potentially damaging circuits that have already met timing. Therefore, an effective software tool must be proposed to improve design performance, inherit existing results, and facilitate team-based design. FPGA vendors have recognized this demand and developed corresponding software tools for logic locking and incremental design. For example, Xilinx’s solution is PlanAhead.
PlanAhead allows high-level designers to designate corresponding FPGA chip areas for different modules and enables lower-level designers to independently design, implement, and optimize within the given areas. Once all modules are correct, design integration is performed. If errors occur during design integration, only the affected module needs modification, without impacting other modules. PlanAhead perfectly combines structured design methods, collaborative team design methods, and reusable inherited design methods, significantly improving design efficiency and shortening design cycles.
However, as described, the new design method places high demands on system-level designers. In the early design stages, they must not only assess the resources consumed by each sub-module but also provide corresponding timing relationships; in the later design stages, they need to complete necessary revisions based on the implementation status of lower-level modules.
4.1 Typical FPGA Development Process and Considerations
The FPGA design process is the procedure of developing FPGA chips using EDA development software and programming tools. A typical FPGA development process generally includes the steps of function definition/device selection, design input, functional simulation, synthesis optimization, post-synthesis simulation, implementation, post-layout simulation, board-level simulation, and chip programming and debugging.
1. Function Definition/Device Selection
Before starting an FPGA design project, a system function definition and module division must be established. Additionally, according to task requirements, such as system functionality and complexity, trade-offs must be made regarding working speed, device resources, costs, and routing feasibility to choose appropriate design schemes and device types. Generally, a top-down design method is adopted, dividing the system into several basic units and then further dividing each basic unit into the next level’s basic units until EDA component libraries can be directly utilized.
2. Design Input
Design input is the process of representing the designed system or circuit in a form required by development software and inputting it to EDA tools. Common methods include Hardware Description Language (HDL) and schematic input methods. The schematic input method is the most direct way of description and was widely used in the early applications of programmable chips, where required components are retrieved from the component library to draw the schematic. Although this method is intuitive and easy to simulate, its efficiency is low, and it is not easy to maintain, making module construction and reuse difficult. More importantly, its portability is poor; when the chip is upgraded, all schematics require modifications. Currently, the most widely used method in practical development is HDL input, which utilizes text descriptions for design and can be divided into ordinary HDL and behavioral HDL. Ordinary HDL includes ABEL, CUR, etc., supporting expressions such as logic equations, truth tables, and state machines, mainly used for simple small designs. For medium to large projects, behavioral HDL is primarily used, with mainstream languages being Verilog HDL and VHDL. Both languages are standards of the Institute of Electrical and Electronics Engineers (IEEE), sharing prominent features: language independence from chip processes, facilitating top-down design, easy module division and portability, good portability, strong logical description and simulation capabilities, and high input efficiency. In addition to these IEEE standard languages, there are vendor-specific languages. A hybrid design approach can also be used, primarily based on HDL and supplemented by schematics to leverage both methods’ strengths.
3. Functional Simulation
Functional simulation, also known as pre-simulation, is the logical functionality verification of the user-designed circuit before compilation. At this stage, the simulation does not include delay information and only tests the preliminary functionality. Before simulation, waveform files and test vectors (i.e., sequences of input signal combinations of interest) must be established using waveform editors and HDL. The simulation results will generate report files and output signal waveforms, from which the changes in signals at various nodes can be observed. If errors are found, the design must be returned for logical modification. Common tools include Model Tech’s ModelSim, Synopsys’s VCS, and Cadence’s NC-Verilog and NC-VHDL.
4. Synthesis Optimization
Synthesis refers to the process of transforming higher-level abstract descriptions into lower-level descriptions. Synthesis optimization optimizes the generated logical connections according to objectives and requirements, flattening hierarchical designs to be implemented by FPGA layout and routing software. Currently, synthesis optimization (Synthesis) refers to compiling design input into a logic connection netlist composed of basic logic units such as AND gates, OR gates, NOT gates, RAM, and flip-flops, rather than actual gate-level circuits. Actual gate-level circuits require using the FPGA manufacturer’s layout and routing functions to produce them based on the synthesised standard gate-level structure netlist. To convert to a standard gate-level structure netlist, the HDL program must comply with the style required by specific synthesizers. Since gate-level and RTL-level HDL program synthesis is a mature technology, all synthesizers can support this level of synthesis. Common synthesis tools include Synplicity’s Synplify/Synplify Pro software and various FPGA manufacturers’ own synthesis development tools.
5. Post-Synthesis Simulation
Post-synthesis simulation checks whether the synthesis results are consistent with the original design. During simulation, the standard delay files generated during synthesis are re-annotated to the synthesized simulation model to estimate the impact of gate delays. However, this step cannot estimate line delays, so there is a certain gap between it and the actual situation after routing, making it not entirely accurate. Currently, synthesis tools are quite mature, and for general designs, this step can be omitted. However, if inconsistencies between the circuit structure and design intent are found after layout and routing, it is necessary to revert to post-synthesis simulation to confirm where the problem lies.
Figure 4-1 Typical FPGA Design Process
6. Implementation and Layout Routing
Layout routing can be understood as using implementation tools to map logic to the resources of the target device structure, determining the optimal layout for logic, selecting routing channels for connections with input/output functions, and generating corresponding files (such as configuration files and related reports). Implementation is the process of configuring the logic netlist generated during synthesis to a specific FPGA chip, with layout routing being the most critical part. Layout will reasonably allocate hardware primitives and lower-level units from the logic netlist onto the chip’s inherent hardware structure, often requiring a choice between speed optimization and area optimization. Routing connects various components correctly and reasonably using the various wiring resources inside the chip based on the layout’s topological structure. Currently, FPGA structures are very complex, especially under timing constraint conditions, requiring the use of timing-driven engines for layout routing. After routing is complete, the software tool will automatically generate reports providing information about resource usage in various parts of the design. Since only FPGA chip manufacturers have the best understanding of chip structures, layout routing must use tools provided by chip developers.
7. Timing Simulation
Timing simulation, also known as post-simulation, refers to the process of re-annotating the delay information from layout routing onto the design netlist to check for any timing violations (i.e., not meeting timing constraints or inherent timing rules of the device, such as setup time, hold time, etc.). Timing simulation contains the most complete and precise delay information and can reflect the actual working conditions of the chip well. Since different chips have different internal delays, different layout routing schemes also have varying impacts on delays. Therefore, it is very necessary to perform timing simulation on the system and each module after layout routing to analyze timing relationships, estimate system performance, and check and eliminate race conditions. The software tools introduced in functional simulation generally support post-synthesis simulation.
8. Board-Level Simulation and Verification
Board-level simulation is mainly applied in high-speed circuit designs to analyze characteristics such as signal integrity and electromagnetic interference in high-speed systems, generally using third-party tools for simulation and verification.
9. Chip Programming and Debugging
The final step of the design is chip programming and debugging. Chip programming refers to generating the data file to be used (bitstream generation) and then downloading the programming data to the FPGA chip. Chip programming must meet certain conditions, such as programming voltage, programming timing, and programming algorithms. Logic analyzers (LA) are the main debugging tools for FPGA design, but they require exposing a large number of test pins, and LA can be expensive. Currently, mainstream FPGA chip manufacturers provide embedded online logic analyzers (such as ChipScope in Xilinx ISE, SignalTapII in Altera QuartusII, and SignalProb) to resolve these conflicts, requiring only a small amount of chip logic resources, which have high practical value.
4.2 FPGA-Based SOC Design Method
Currently, with the improvement in FPGA performance and the drop in prices, along with the increasing number of embedded cores, many IC design companies are naturally using FPGAs for ASIC prototype verification, bringing the programmable advantages of FPGAs into the SOC field, which consists of embedded processor cores, DSP units, large-capacity processors, gigabit transceivers, mixed logic, IP, and existing design parts.
The core part of the SOC platform is the embedded processing core, where the hardware is fixed and the software is programmable; the peripheral circuits consist of the logic resources of the FPGA, mostly provided in the form of IP, such as memory interfaces, USB interfaces, and Ethernet MAC layer interfaces, allowing users to add and customize corresponding interface IP and peripherals based on their needs.
The typical SOC development process based on FPGA includes:
1. Considerations Inside the Chip
From the start of design generation, designers need to approach from a hardware/software co-verification perspective to identify soft and hard defects that can only be discovered during the system integration phase. Then, they select appropriate chips and development tools, optimize during synthesis, and subsequently carry out precise implementation to meet actual requirements. As design scales increase and working frequencies reach hundreds of megahertz, layout routing delays become very important. To ensure timing requirements are met, static timing analysis should be performed after layout routing to verify the design.
2. Board-Level Verification
After the chip design is completed, board-level verification must be conducted to ensure consistency with the original design functionality on the printed circuit board (PCB). Therefore, PCB layout and signal integrity testing should be included in the design process. Any changes made in the chip design will reflect in the downstream design processes, and data interfaces and management between various processes must be error-free. It is expected that the SOC system and necessary additional processes will exponentially increase the size of data, making managing various datasets a dramatically challenging task.
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