Outstanding IC/FPGA Open Source Projects [Part 1]

Google OpenTitan

https://github.com/lowRISC/opentitan

OpenTitan aims to make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is a collaborative project managed by lowRISC CIC to produce high-quality open IP as instances of full-function products. This repository exists to facilitate collaboration among partners involved in the OpenTitan project;

Official website: https://opentitan.org/ Documentation link: https://docs.opentitan.org/

openwifi

https://github.com/open-sdr/openwifi-hw

The first open-source Wi-Fi baseband chip:

Includes hardware/FPGA design. Used with openwifi (drivers and software tools).

Precompiled FPGA files: boards/ $BOARD_NAME /sdk/ contains FPGA bit, ila .ltx files, and other initialization files.

Environment variable BOARD_NAME options:

• zc706_fmcs2 (Xilinx ZC706 board + FMCOMMS2/3/4)
• zed_fmcs2 (Xilinx zed board + FMCOMMS2 /3/4)
• adrv9364z7020 (ADRV9364-Z7020 + ADRV1CRR -BOB)
• adrv9361z7035 (ADRV9361-Z7035 + ADRV1CRR-BOB/FMC)
• zc702_fmcs2 (Xilinx ZC702 board + FMCOMMS2 /3/4)
• antsdr (MicroPhase enhanced ADALM -PLUTO SDR. Note)
• zcu102_fmcs2 (Xilinx ZCU102 board + FMCOMMS2/3/4)

platformio-core

https://github.com/platformio/platformio-core

PlatformIO is a professional embedded development collaboration platform;

• Open source, licensed under Apache 2.0
• Cross-platform IDE and unified debugger
• Static code analyzer and remote unit testing
• Multi-platform multi-architecture build system
• Firmware file resource manager and memory inspection

SM3_core

https://github.com/ljgibbslf/SM3_core

SM3 is China’s hash cryptographic algorithm national standard. The SM3 algorithm belongs to hash algorithms, similar to SHA and MD5, and is also known as hash function, hash algorithm, etc.

The SM3 hash algorithm is independently developed in China and was elevated to national standard in 2016.

SM3 algorithm uses Merkle-Damgård structure, message block length of 512 bits, and summary result length of 256 bits. The SM3 algorithm includes three steps: message padding, message expansion, and message compression.

The overall structure is similar to SHA-256 algorithm structure, but adds various new design techniques to enhance security.

• Version 0.2, supports 64-bit bus, and has been performance analyzed on FPGA platform, with maximum throughput close to 2Gbps.

• Version 0.3, added preliminary support for open-source simulator EpicSim and provided example simulation scripts

wujian100_open

https://github.com/ehello/wujian100_open

Alibaba Pingtouge’s open-source RISC-V project

aws-fpga

https://github.com/aws/aws-fpga

AWS EC2 FPGA Development Kit is a set of development and runtime tools for developing, simulating, debugging, compiling, and running hardware-accelerated applications on Amazon EC2 F1 instances. It is distributed between this GitHub and AWS provided FPGA Developer AMI – Centos / AL2, with no development tool costs.

clash-compiler

https://github.com/clash-lang/clash-compiler

Clash is a functional hardware description language that draws on the syntax and semantics of the functional programming language Haskell. The Clash compiler converts these high-level descriptions into synthesizable low-level VHDL, Verilog, or SystemVerilog.

Features:

• Strongly typed, but with very high type inference, achieving safe and fast prototyping with concise descriptions.
• Interactive REPL: Load your designs in the interpreter and easily test all components without setting up a test bench.
• Higher-order functions with type inference lead to designs that are fully parameterized by default.
• Design of synchronous timing circuits based on a value flow called Signals leads to a natural description of feedback loops.
• Support for multiple clock domains with type-safe clock domain crossing.

NVDLA hw

https://github.com/nvdla/hw

NVIDIA Deep Learning Accelerator (NVDLA) is a free open architecture that facilitates the standard approach to designing deep learning inference accelerators. With its modular architecture, NVDLA is scalable, highly configurable, and designed to simplify integration and portability;

Includes RTL, C models, and testbench code related to NVDLA hardware versions;

tinyriscv

https://gitee.com/liangkangnan/tinyriscv

A small RISC-V processor core, a single-core 32-bit small RISC-V processor core written in Verilog. The design goal is to match the ARM Cortex-M3 series processors. tinyriscv has the following features:

• Supports RV32IM instruction set, compatible with RISC-V instruction compatibility testing;
• Uses a three-stage pipeline: instruction fetch, decode, execute;
• Can run C language programs;
• Supports JTAG, can read and write memory (online program updates) through openocd;
• Supports interrupts;
• Supports buses;
• Supports FreeRTOS;
• Supports program updates via serial port;
• Easy to port to any FPGA platform;